Vehicle State and Friction Force Estimation Based on FPGA

2013 ◽  
Vol 336-338 ◽  
pp. 999-1002
Author(s):  
Lin Hui Zhao ◽  
Zhi Yuan Liu
Keyword(s):  
Friction Force ◽  
Estimation Algorithm ◽  
Nonlinear Observer ◽  
Force Estimation ◽  
Verilog Hdl ◽  
Description Language ◽  
Computational Performance ◽  
Field Programmable ◽  
Hardware Description ◽  
System On Programmable Chip

In order to improve the computational performance of the nonlinear observer for vehicle state and friction force estimation, two novel implementation schemes in Verilog Hardware Description Language (HDL) and System on Programmable Chip (SoPC) is proposed based on Field Programmable Gate Array (FPGA). Firstly, the parallelism analysis of the vehicle state and friction force estimation algorithm is provided. Then, the Verilog HDL and SoPC implementation schemes are presented respectively based on the analysis results. Finally, a testing platform is built to evaluate the functionality and the computational performance of the implementation schemes. The experimental results show that the proposed schemes all have high precision and computational efficiency for vehicle state and friction force estimation.

scholarly journals Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm

2022 ◽  
Vol 10 (5) ◽  
pp. 57-60
Author(s):  
B Murali Krishna ◽  
◽  
B.T. Krishna ◽  
K Babulu ◽  
◽  
...  
Keyword(s):  
Cordic Algorithm ◽  
Matlab Simulation ◽  
Verilog Hdl ◽  
Description Language ◽  
S Transform ◽  
Field Programmable ◽  
Hardware Resource ◽  
Linear Transform ◽  
Hardware Description ◽  
Stockwell Transform

A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.

scholarly journals Adaptive Nonlinear Tire-Road Friction Force Estimation for Vehicular Systems Based on a Novel Differentiable Friction Model

2015 ◽  
Vol 2015 ◽  
pp. 1-7 ◽  
Author(s):  
Zhi-Jun Fu ◽  
Wei-Dong Xie ◽  
Xiao-Bin Ning
Keyword(s):  
Friction Force ◽  
Estimation Algorithm ◽  
Friction Model ◽  
Lyapunov Theory ◽  
Nonlinear Observer ◽  
Estimation Methods ◽  
Vehicle Speed ◽  
Force Estimation ◽  
Observer Error ◽  
Road Friction

A novel adaptive nonlinear observer-based parameter estimation scheme using a newly continuously differentiable friction model has been developed to estimate the tire-road friction force. The differentiable friction model is more flexible and suitable for online adaptive identification and control with the advantage of more explicit parameterizable form. Different from conventional estimation methods, the filtered regression estimation parameter is introduced in the novel adaptive laws, which can guarantee that both the observer error and parameter error exponentially converge to zero. Lyapunov theory has been used to prove the stability of the proposed methods. The effectiveness of the estimation algorithm is illustrated via a bus simulation model in the Trucksim software and simulation environment. The relatively accurate tire-road friction force was estimated just by the easily existing sensors signals wheel rotational speed and vehicle speed and the proposed method also displays strong robustness against bounded disturbances.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

Implementation of CRC by Using FPGA in Data Communication

2013 ◽  
Vol 325-326 ◽  
pp. 1805-1808
Author(s):  
Lie Wang ◽  
Yi Jie Wang
Keyword(s):  
Hardware Implementation ◽  
Data Communication ◽  
Communication Process ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Communication Structure ◽  
Development Platform ◽  
Hardware Description ◽  
Analyze Data

By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It also benefits hardware implementation.

New Hardware Architecture for Self-Organizing Map Used for Color Vector Quantization

2019 ◽  
Vol 29 (01) ◽  
pp. 2050002
Author(s):  
Khaled Ben Khalifa ◽  
Ahmed Ghazi Blaiech ◽  
Mehdi Abadi ◽  
Mohamed Hedi Bedoui
Keyword(s):  
Vector Quantization ◽  
Recent Literature ◽  
Network Architectures ◽  
Self Organizing Map ◽  
Description Language ◽  
Field Programmable ◽  
Color Vector ◽  
Hardware Description ◽  
Som Network ◽  
Self Organizing

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [Formula: see text] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

scholarly journals Design, Simulation and Implementation of an Active Sound-Noise Cancellation System for Use in a Cockpit Intercommunication System

2012 ◽  
Vol 10 (5) ◽  
Author(s):  
O. Sharifi-Tehrani
Keyword(s):  
Active Noise Control ◽  
Description Language ◽  
Noise Sources ◽  
Electronic Warfare ◽  
Active Structure ◽  
Hardware Description ◽  
Adaptive Noise ◽  
System On Programmable Chip ◽  
And Performance

In this paper, an active noise control system for denoising the intercommunication signal of an airplane cockpit isproposed. Noise sources such as engines degrade the quality of the intercommunication signal, especially in the caseof the pilot and copilot headsets. A two-microphone active adaptive noise controller is designed by using an adaptiveFIR filter in an active structure. The designed system is simulated and also implemented in real environment usingreal speech signals, periodic noise and AWGN noise. Also, an FPGA-based hardware implementation utilizing a novelmethod is provided. The whole design is considered an FPGA hardware core with low resource utilizations which issuitable for HW/SW codesign and System-on-Programmable-Chip (SoPC) applications. The codes have been writtenby using the VHDL93 hardware description language, the XilKernel embedded operating system and a finite statemachine. The obtained results showed competent functionality and performance of the proposed system. This ICSnoise removal architecture can be used on any cargo, civil or fighter platform (such as C-130, IR-AN 140 and F5-F)and also in radar and electronic warfare (EW) systems (for clutter/interference compensation) with minimum hardwareor software changes.

scholarly journals PROJECT DESIGN FOR COMPUTER ARCHITECTURE PRACTICAL SESSIONS BASED ON FIELD-PROGRAMMABLE GATE ARRAY

2021 ◽  
Vol 13 (0) ◽  
pp. 1-5
Author(s):  
Kęstutis Bartnykas
Keyword(s):  
Computer Architecture ◽  
Project Design ◽  
Electronic Systems ◽  
Programmable Logic Arrays ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Design Ideas ◽  
Dedicated Processors ◽  
Dedicated Processor

Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according to the provided specification during a certain number of projects. The weakness of this approach is that the basis of such projects is a processor of one specific architecture, so the lecturer faces the issue of individualization of projects. This article proposes a solution based on dedicated processors instead of one programmable processor of a specific architecture. It’s shown here that the issue of project individualization is easier solvable in the proposed way, and it does not deviate from the theory of computer architecture, because the programmable processor is a generalization of a dedicated processor. The article describes project design ideas based on dedicated processors and gives some examples. Represented different instance than was applied during practical sessions of Computer Architecture that are held at the Department of Electronic Systems within VILNIUS TECH, i.e. certain modifications, and additions were applied.

scholarly journals A Real Time Algorithm for Versatile Mode Parking System and Its Implementation on FPGA Board

2022 ◽  
Vol 12 (2) ◽  
pp. 655
Author(s):  
Baligh Naji ◽  
Chokri Abdelmoula ◽  
Mohamed Masmoudi
Keyword(s):  
Real Time ◽  
Evaluation Process ◽  
Time Algorithm ◽  
Hardware Description Language ◽  
Optimal Solutions ◽  
Description Language ◽  
Parking System ◽  
Parking Lot ◽  
Field Programmable ◽  
Hardware Description

This paper presents the design and development of a technique for an Autonomous and Versatile mode Parking System (AVPS) that combines a various number of parking modes. The proposed approach is different from that of many developed parking systems. Previous research has focused on choosing only a parking lot starting from two parking modes (which are parallel and perpendicular). This research aims at developing a parking system that automatically chooses a parking lot starting from four parking modes. The automatic AVPS was proposed for the car-parking control problem, and could be potentially exploited for future vehicle generation. A specific mode can be easily computed using the proposed strategy. A variety of candidate modes could be generated using one developed real time VHDL (VHSIC Hardware Description Language) algorithm providing optimal solutions with performance measures. Based on simulation and experimental results, the AVPS is able to find and recognize in advance which parking mode to select. This combination describes full implementation on a mobile robot, such as a car, based on a specific FPGA (Field-Programmable Gate Array) card. To prove the effectiveness of the proposed innovation, an evaluation process comparing the proposed technique with existing techniques was conducted and outlined.

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