Design of High-Speed Communication on the Detection Equipment

2014 ◽  
Vol 496-500 ◽  
pp. 1390-1393
Author(s):  
Wei Xin Zhang ◽  
Wei Bing Bai ◽  
Lin Tao Li ◽  
Ji Wen Hu ◽  
Chao Feng
Keyword(s):  
Fault Diagnosis ◽  
Transmission Lines ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Serial Communication ◽  
Digital Processing ◽  
Field Programmable ◽  
Fault Diagnosis System ◽  
Common Signal ◽  
Transmission Speed

After the equipment of a new equipment, the cambat effectiveness has been greatly improved. The lack of a intelligent fault diagnosis system delayed the generation of equipment support ability, so a kind of detection equipment which can intelligently and quickly diagnose the fault was urgently needed .Based on the field programmable gate array (FPGA) and ARM platform, this paper gives a design of a high-speed digital processing detector. Using the serial communication, it can not only transmit a variety of common signal at a high speed, but also eliminate the interference between the transmission lines. As serial communication has no synchronous problem, there's more room to improve the transmission speed.

Research on Internet-Based Reconfigurable Distance Mechanical System Fault Diagnosis

2011 ◽  
Vol 52-54 ◽  
pp. 109-114
Author(s):  
Yun Jie Xu
Keyword(s):  
Fault Diagnosis ◽  
Mechanical System ◽  
High Speed ◽  
Structural Model ◽  
Component Technology ◽  
The Internet ◽  
Diagnostic Systems ◽  
Diagnosis System ◽  
J2ee Framework ◽  
Fault Diagnosis System

In order to meet requirements of increasingly high-speed, large and intelligent mechanical equipments on fault diagnosis, the Internet-based reconfigurable mechanical system fault diagnosis program was presented. The overall structure and networking schema of distance mechanical fault diagnosis system were analyzed, and the distance fault diagnosis network model based on J2EE framework was also described. The structural model and reconfigurable manner of the reconfigurable distance diagnosis system was provided, which used CORBA component technology to achieve reconfiguration. The detail steps of system that take some type of diesel engine as diagnosis object was described, and the intelligent diagnosing methods were also researched. The Internet-based fault diagnosis technology effectively improves the efficiency and accuracy of diagnostic systems.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

High Speed Under-Sampling Frequency Measurements on FPGA

2017 ◽  
Vol 7 (3) ◽  
pp. 1316
Author(s):  
Seyed Ehsan Yasrebi Naeini ◽  
Ali Maroosi
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Sampling Rate ◽  
Sampling Frequency ◽  
Phase Changes ◽  
Frequency Measurements ◽  
Frequency Detection ◽  
Field Programmable ◽  
Under Sampling ◽  
Nyquist Rate

A Sampling rate is less than Nyquist rate in some applications because of hardware limitations. Consequently, extensive researches have been conducted on frequency detection from sub-sampled signals. Previous studies on under-sampling frequency measurements have mostly discussed under-sampling frequency detection in theory and suggested possible methods for fast under-sampling frequencies detection. This study examined few suggested methods on Field Programmable Gate Array (FPGA) for fast under-sampling frequencies measurement. Implementation of the suggested methods on FPGA has issues that make them improper for fast data processing. This study tastes and discusses different methods for frequency detection including Least Squares (LS), Direct State Space (DSS), Goertzel filter, Sliding DFT, Phase changes of Fast Furrier Transform (FFT), peak amplitude of FFT to conclude which one from these methods are suitable for fast under-sampling frequencies detection on FPGA. Moreover, our proposed approach for sub-sampling detection from real waveform has less complextity than previous approaches from complex waveform.

Design and Test of High Speed Digitization Sampling Circuit Based on FPGA

2013 ◽  
Vol 482 ◽  
pp. 386-389
Author(s):  
Peng Qin ◽  
Hao Lu ◽  
Zhi Ye Jiang ◽  
Jin Liang Bai ◽  
Lu Gao ◽  
...  
Keyword(s):  
Data Acquisition ◽  
Circuit Design ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Engineering Practice ◽  
Excellent Performance ◽  
Field Programmable ◽  
High Speed Data Acquisition ◽  
High Speed Data ◽  
Data Acquisition Program

To sample wideband IF signal with large amounts of data, a high-speed data acquisition program is presented. The program focus on circuit design, issues that need attention, and high-speed sampling signal deceleration strategy. The 2.4GHz rate sampling data acquisition, reception and demux are completed with ADC083000 and Field-Programmable Gate Array (FPGA). At last, a result of sampling with the converter is offered by chipscope software. The result verified ADC083000 has an excellent performance with more than 6.5 bit ENOB and good phase coherence. In engineering practice, the design has been used and has good performance.

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