An Improved Estimation of Distribution Algorithm for Dynamic Voltage Scaling Problem in Heterogeneous System

2014 ◽  
Vol 631-632 ◽  
pp. 373-377 ◽  
Author(s):  
Yan Kang ◽  
Zhong Min Wang ◽  
Ying Lin ◽  
Yi Fan Zhang
Keyword(s):  
Supply Voltage ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Estimation Of Distribution Algorithm ◽  
Distributed Embedded Systems ◽  
Dynamic Voltage ◽  
Estimation Of Distribution ◽  
Operational Frequency ◽  
Evolutionary Operators ◽  
Global And Local

Energy consumption can be optimized by utilizing dynamic voltage scaling that conjointly adjusts the supply voltage and the operational frequency during the execution of the tasks to effectively minimize the energy. An improved estimation of distribution algorithm is presented for energy saving of the distributed embedded systems that consists of dynamic voltage scalable processing elements. The algorithm evolves computation by using the univariate marginal distribution to search the solution in a discrete space and mapping the solutions into feasible ones stratified the precedence constraint. The algorithm hybridize the genetic algorithm with estimation of distribution algorithm by combines statistically learning and sampling the probability distribution of the population iteratively and the conventional evolutionary operators such as crossover and mutation together. Simulated annealing is utilized to accept some bad solution rather the elite solution to make fully use of the global and local information. Experiments are implemented to demonstrate the performance of the algorithm

A 16Kb SRAM with Programmable Replica Bitlines for Dynamic Voltage Scaling Systems

2012 ◽  
Vol 542-543 ◽  
pp. 416-422
Author(s):  
Ming Qiang Qiu ◽  
Na Bai ◽  
Jian Meng ◽  
Jun Ning Chen
Keyword(s):  
Supply Voltage ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Discharge Time ◽  
Test Chip ◽  
Voltage Range ◽  
Low Leakage ◽  
Dynamic Voltage ◽  
Operational Frequency ◽  
The Cost

The SRAM applied to dynamic voltage scaling systems has a problem that the differential voltage of the bitlines (ΔVBL) increases as the supply voltage rises with the conventional replica bitlines technique, and the increased ΔVBL degrades the SRAM performance and dissipates more power. In this paper, a programmable replica bitlines technique is presented to resolve the problem. With the new technique we acquired bitline discharge time reduction up to 25.3% at the cost of 0.6% area penalty in a 16Kb SRAM. The 16Kb SRAM test chip is fabricated by using 65nm low leakage technology. Testing results show that the maximum operational frequency of the SRAM is improved from 4.3% to 9.5% under the voltage range of 0.8V~1.4V comparing with the conventional one. The operating frequency of the SRAM with proposed technique is from 440MHz at 0.8V to 1.62GHz at1.4V.

ADAPTIVE DELAY CORRECTION FOR RUNTIME VARIATION IN DYNAMIC VOLTAGE SCALING SYSTEMS

2008 ◽  
Vol 17 (06) ◽  
pp. 1111-1128 ◽  
Author(s):  
DAVID WOLPERT ◽  
PAUL AMPADU
Keyword(s):  
Supply Voltage ◽  
Process Variation ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Ring Oscillator ◽  
New Method ◽  
Lookup Table ◽  
Worst Case ◽  
Dynamic Voltage ◽  
Delay Sensitivity

Temperature and voltage fluctuations affect delay sensitivity differently, as supply voltage is reduced. These differences make runtime variations particularly difficult to manage in dynamic voltage scaling systems, which adjust supply voltage in accordance with the required operating frequency. To include process variation in current table-lookup methods, a worst-case process is typically assumed. We propose a new method that takes process variation into account and reduces the excessive runtime variation guardbands. Our approach uses a ring oscillator to generate baseline frequencies, and employs a guardband lookup table to offset this baseline. The new method ensures robust operation and reduces power consumption by up to 20% compared with a method that assumes worst-case process variation in filling a lookup table.

scholarly journals Comparison of Dynamic Voltage Scaling (DVS) of Core Voltage Using the On-board Voltage Regulator and External Voltage Regulator via I2C Protocol in Automotive Micro controller

2021 ◽  
Vol 23 (06) ◽  
pp. 794-804
Author(s):  
Kiran Guruprasad Shetty P S ◽  
◽  
Dr. Ravish Aradhya H V ◽  
Eswar Goda ◽  
◽  
...  
Keyword(s):  
Power Management ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Voltage Regulator ◽  
External Voltage ◽  
The Core ◽  
Control Command ◽  
Dynamic Voltage

Dynamic Voltage Scaling is performed on automotive micro-controller AURIX from Infineon Technologies. In this micro-controller the core and different IPs operate on the 1.25 V supply rail, so dynamically voltage is changed according to the workload in the micro-controller. DVS is done either using an internal onboard voltage regulator or an external voltage regulator. An External board (KITPF3000FRDMEV), which has a controller and a Power Management Integrated Circuit (PMIC) is used for changing the supply voltage to the micro-controller during DVS using an external voltage regulator. The micro-controller is predicting the workload and according to workload, the control command is sent to the controller (FRDM-KL25) in the kit through I2C communication and then the controller sends the command to adjust the voltage of PMIC (PF3000) through I2C communication. Both current measurements for the internal voltage regulator and external voltage regulator are measured for various loads and latency is measured for various baud rates while using external voltage regulator through I2C protocol.

DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE

2008 ◽  
Vol 17 (05) ◽  
pp. 871-883 ◽  
Author(s):  
SAMI KIROLOS ◽  
YEHIA MASSOUD
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Minimum Energy ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Size Ratio ◽  
Ring Oscillator ◽  
Subthreshold Region ◽  
Wide Range ◽  
Dynamic Voltage

In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

ENERGY-CONSTRAINED VDD HOPPING SCHEME WITH RUN-TIME POWER ESTIMATION FOR LOW-POWER REAL-TIME VLSI SYSTEMS

2002 ◽  
Vol 11 (06) ◽  
pp. 601-620 ◽  
Author(s):  
SEONGSOO LEE ◽  
SEUNGJUN LEE ◽  
TAKAYASU SAKURAI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Voltage Scaling ◽  
Dynamic Voltage Scaling ◽  
Multimedia Applications ◽  
Variable Voltage ◽  
Dynamic Voltage ◽  
Energy Constrained ◽  
Variable Voltage Processor

In this paper, we propose a novel dynamic voltage scaling algorithm on a variable-voltage processor. It determines the supply voltage on timeslot-by-timeslot basis within the task boundary, and significantly reduces the power consumption by fully exploiting the slack time. Also, we modify this algorithm and propose an energy-constrained dynamic voltage scaling algorithm for low-power multimedia applications. In the multimedia applications, there are usually several alternative algorithms with different performance and power. Considering the trade-off between performance and power, the proposed algorithm adaptively determines the optimal alternative to achieve optimal performance under given energy constraint. Compared with the conventional algorithms, the power consumption is reduced to 1/14.4 ~ 1/5.6 without performance degradation.

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