Three Parametric Model Third-Order Software Phase-Locked Loop and its Application in Range Measuring System

2011 ◽  
Vol 383-390 ◽  
pp. 5250-5256
Author(s):  
Xiao Min Hou ◽  
Yun Wang

In order to improve the precision of side tone range measuring and realize the range measuring process by software, one kind of three parametric model third-order software phase-locked loop (SPLL) is designed based on three parametric loop filter model and the predominant closed-loop poles theory, which can apply the parameter setting principles of the second-order phase-locked loop; this kind of third-order SPLL is realized through C++ language programming and used as the range measuring system’s side tone phase-locked loop(PLL) to process the experiment data. The results indicates that the precision of phase measuring and capture time satisfy the system’s index.

2013 ◽  
Vol 756-759 ◽  
pp. 2192-2196
Author(s):  
Lan Ying Zhang ◽  
Hai Yang Liu ◽  
Hong Yin Du

The mathematic model of third-order software phase locked loop formed by three-parameter loop filter is analyzed and designed. Then, in order to solve the problem of redundancy frequency analysis bandwidth when carrier tracking, a variable data ratio software phase locked loop is studied. Finally, the method is simulated and analyzed. The simulation results demonstrate that the software phase locked loop with variable data ratio can effectively reduce the operation capacity and improve the management efficiency of the software phase locked loop.


Author(s):  
Baoling Guo ◽  
Seddik Bacha ◽  
Mazen Alamir ◽  
Julien Pouget

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.


2014 ◽  
Vol 43 (6) ◽  
pp. 776-792 ◽  
Author(s):  
Madhab Chandra Tripathy ◽  
Debasmita Mondal ◽  
Karabi Biswas ◽  
Siddhartha Sen

Author(s):  
P.N. Metange ◽  
K. B. Khanchandani

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>


2007 ◽  
Vol E90-C (6) ◽  
pp. 1197-1202
Author(s):  
S. DOSHO ◽  
N. YANAGISAWA ◽  
K. SOGAWA ◽  
Y. YAMADA ◽  
T. MORIE

2017 ◽  
Vol 31 (07) ◽  
pp. 1741010 ◽  
Author(s):  
Ji Lei ◽  
Meng Hui Zhi ◽  
Xin Wei Li ◽  
Tang Liang ◽  
Dong Hai Qiao

Nowadays, some countries have already invented chip-scale atomic clock (CSAC) based on coherent population trapping (CPT), and it has been applied in every areas. According to its working principle, the microwave signal source is one of the decisive factors affecting its stability. Usually the microwave signal source is a phase-locked loop circuit, it mainly includes a frequency synthesizer, a voltage controlled oscillator (VCO) and a loop filter. This paper aims to develop a microwave signal source for Cs CSAC. First, a VCO should be designed, in order to validate the characteristic of the designed VCO, the VCO needs to be tested at high and low temperatures, and the results show that it has good stability of high and low temperatures. Second, for the purpose of verifying that the design and production consistency of the VCO are in good condition, 1000 VCOs are test, respectively. The statistical distribution of the phase noise at 1 kHz offset would be painted a curve. Finally, the designed VCO (PN: 61.01dBc/Hz@1kHz) will be applied in phase-locked loop, the test results show that the phase noise is −83.57dBc/Hz@300Hz, it is much better than −43dBc/Hz@300Hz which is the spec of CSAC. If the microwave signal source would be used in CSAC, its stability would be greatly improved.


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