scholarly journals A SIMULATION MODEL FOR ROBOT’S SLIP DISPLACEMENT SENSORS

2016 ◽  
pp. 224-236 ◽  
Author(s):  
Yuriy Kondratenko ◽  
Oleksandr Gerasin ◽  
Andriy Topalov
Keyword(s):  
Simulation Model ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Displacement Sensor ◽  
Clamping Force ◽  
Sensing System ◽  
Displacement Sensors ◽  
Field Programmable ◽  
Slip Displacement ◽  
Corrosive Environments

This paper deals with a simulation model of slip displacement sensors for the object slip signals’ registration in the adaptive robot’s gripper. The study presents the analysis of different methods for slip displacement signals detection, as well as authors’ solutions. Special attention is paid to the investigations of the developed sensor with the resistive registration element in rod type structure of sensitive elements, which is able to operate in harsh and corrosive environments. A sensing system for the object slip signals’ registration in the adaptive robot’s gripper with a clamping force correction is developed for proposed slip displacement sensor with multi-component resistive registration elements. The hardware implementation of the sensing system for slip signals’ registration and obtained results are considered in details. The simulation model of the proposed slip displacement sensor based on polytypic conductive rubber is modeled by Proteus software. The intelligent approaches with the use of a field programmable gate array (FPGA) and VHDL-model to the sensing system designing allow to define the slippage direction in slip displacement sensor based on resistive registration elements. Thus, this expands the functionality of the developed sensor.

Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

scholarly journals Bubble-Proof Algorithm for Wave Union TDCs

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 30
Author(s):  
Paweł Kwiatkowski ◽  
Dominik Sondej ◽  
Ryszard Szplet
Keyword(s):  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Single Shot ◽  
Output Data ◽  
Data Encoding ◽  
Field Programmable ◽  
Output Code ◽  
Efficient Data ◽  
Fpga Chip

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

scholarly journals Simple Hardware Implementation of Motion Estimation Algorithms

2019 ◽  
Vol 11 (3) ◽  
Author(s):  
Juan Romero ◽  
Damien Verdier ◽  
Clement Raffaitin ◽  
Luis Miguel Procel ◽  
Lionel Trojman
Keyword(s):  
Optical Flow ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Software Implementation ◽  
Hardware Description Language ◽  
Successful Implementation ◽  
Description Language ◽  
Estimation Algorithms ◽  
Field Programmable ◽  
Hardware Description

We present in the following work a hardware implementation of the two principal optical flow methods. The work is based on the methods developed by Lucas & Kanade, and Horn & Schunck. The implementation is made by using a field programmable gate array and Hardware Description Language. To achieve a successful implementation, the algorithms were optimized. The results show the optical flow as a vector field over one frame, which enable an easy detection of the movement. The results are compared to a software implementation to insure the success of the method. The implementation is a fast implementation capable of quickly overcoming a traditional implementation in software.

scholarly journals FPGA Implementation of DTCWT and PCA Based Watermarking Technique

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
M. S. Sudha ◽  
T. C. Thanuja
Keyword(s):  
Wavelet Transform ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Implementation ◽  
Image Watermarking ◽  
Software Implementation ◽  
Low Power Consumption ◽  
Complex Wavelet Transform ◽  
System Generator ◽  
Field Programmable

The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.

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