A Novel Integrated MEMS Pyramidal Horn Antenna for Terahertz Applications

2013 ◽  
Vol 760-762 ◽  
pp. 434-437
Author(s):  
Lin Guo ◽  
Feng Yi Huang ◽  
Xu Sheng Tang
Keyword(s):  
High Performance ◽  
Horn Antenna ◽  
Fabrication Cost ◽  
Terahertz Applications ◽  
Mems Technology ◽  
Pyramidal Horn ◽  
On Chip ◽  
Thz Applications ◽  
Thz Antenna

This paper reports the design and analysis of a novel pyramidal horn antenna based on Micro­electromechanical Systems (MEMS) technology, which is used in terahertz (THz) applications. The structure of the antenna includes two parts, pyramidal horn and inverted pyramidal horn for feed, the fabrication of the structure needs only one wafer, and the antenna can be easily integrated with other parts of on-chip circuits. There are many tunable parameters of the horn, so that high performance THz antenna can be achieved by optimizing these parameters. The proposed antenna can be manufactured by MEMS processing with low fabrication cost, suitable for many terahertz systems.

scholarly journals Antenna on Chip (AoC) Design Using Metasurface and SIW Technologies for THz Wireless Applications

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1120
Author(s):  
Ayman A. Althuwayb ◽  
Mohammad Alibakhshikenari ◽  
Bal S. Virdee ◽  
Harry Benetatos ◽  
Francisco Falcone ◽  
...  
Keyword(s):  
High Performance ◽  
Silicon Oxide ◽  
Coplanar Waveguide ◽  
Promising Candidate ◽  
Antenna Structure ◽  
Physical Size ◽  
Wireless Applications ◽  
Effective Aperture ◽  
On Chip ◽  
Thz Antenna

This paper presents the design of a high-performance 0.45–0.50 THz antenna on chip (AoC) for fabrication on a 100-micron GaAs substrate. The antenna is based on metasurface and substrate-integrated waveguide (SIW) technologies. It is constituted from seven stacked layers consisting of copper patch–silicon oxide–feedline–silicon oxide–aluminium–GaAs–copper ground. The top layer consists of a 2 × 4 array of rectangular metallic patches with a row of subwavelength circular slots to transform the array into a metasurface. This essentially enlarges the effective aperture area of the antenna. The antenna is excited using a coplanar waveguide feedline that is sandwiched between the two silicon oxide layers below the patch layer. The proposed antenna structure reduces substrate loss and surface waves. The AoC has dimensions of 0.8 × 0.8 × 0.13 mm3. The results show that the proposed structure greatly enhances the antenna’s gain and radiation efficiency, and this is achieved without compromising its physical size. The antenna exhibits an average gain and efficiency of 6.5 dBi and 65%, respectively, which makes it a promising candidate for emerging terahertz applications.

scholarly journals In-Situ Integration of 3D C-MEMS Microelectrodes with Bipolar Exfoliated Graphene for Label-Free Electrochemical Cancer Biomarkers Aptasensor

Micromachines ◽  
2022 ◽  
Vol 13 (1) ◽  
pp. 104
Author(s):  
Shahrzad Forouzanfar ◽  
Nezih Pala ◽  
Chunlei Wang
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Point Of Care ◽  
High Sensitivity ◽  
Label Free ◽  
Lab On Chip ◽  
Electrochemical Label ◽  
Mems Technology ◽  
On Chip

The electrochemical label-free aptamer-based biosensors (also known as aptasensors) are highly suitable for point-of-care applications. The well-established C-MEMS (carbon microelectromechanical systems) platforms have distinguishing features which are highly suitable for biosensing applications such as low background noise, high capacitance, high stability when exposed to different physical/chemical treatments, biocompatibility, and good electrical conductivity. This study investigates the integration of bipolar exfoliated (BPE) reduced graphene oxide (rGO) with 3D C-MEMS microelectrodes for developing PDGF-BB (platelet-derived growth factor-BB) label-free aptasensors. A simple setup has been used for exfoliation, reduction, and deposition of rGO on the 3D C-MEMS microelectrodes based on the principle of bipolar electrochemistry of graphite in deionized water. The electrochemical bipolar exfoliation of rGO resolves the drawbacks of commonly applied methods for synthesis and deposition of rGO, such as requiring complicated and costly processes, excessive use of harsh chemicals, and complex subsequent deposition procedures. The PDGF-BB affinity aptamers were covalently immobilized by binding amino-tag terminated aptamers and rGO surfaces. The turn-off sensing strategy was implemented by measuring the areal capacitance from CV plots. The aptasensor showed a wide linear range of 1 pM–10 nM, high sensitivity of 3.09 mF cm−2 Logc−1 (unit of c, pM), and a low detection limit of 0.75 pM. This study demonstrated the successful and novel in-situ deposition of BPE-rGO on 3D C-MEMS microelectrodes. Considering the BPE technique’s simplicity and efficiency, along with the high potential of C-MEMS technology, this novel procedure is highly promising for developing high-performance graphene-based viable lab-on-chip and point-of-care cancer diagnosis technologies.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Design and simulation of high performance router on chip based on random routing

2014 ◽  
Vol 27 (7) ◽  
pp. 669-675 ◽  
Author(s):  
Feng Yue ◽  
Runfeng Li ◽  
Tian Chen ◽  
Jun Liu ◽  
Peng Chen ◽  
...  
Keyword(s):  
High Performance ◽  
On Chip

МЕТОДЫ ДОСТИЖЕНИЯ МАКСИМАЛЬНОЙ ЭФФЕКТИВНОСТИ ПЛАТФОРМЫ ПРОТОТИПИРОВАНИЯ ВЫСОКОПРОИЗВОДИТЕЛЬНЫХ СИСТЕМ НА КРИСТАЛЛЕ НА ЗАДАЧАХ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА

2020 ◽  
Vol 96 (3s) ◽  
pp. 585-588
Author(s):  
С.Е. Фролова ◽  
Е.С. Янакова
Keyword(s):  
Neural Network ◽  
Artificial Intelligence ◽  
Computer Vision ◽  
High Performance ◽  
Systems On Chip ◽  
High Performance Systems ◽  
On Chip ◽  
Network Technologies ◽  
Neural Network Technologies

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Graphene Nanoribbon Gap Waveguides for Dispersionless and Low-Loss Propagation with Deep-Subwavelength Confinement

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1302
Author(s):  
Zhiyong Wu ◽  
Lei Zhang ◽  
Tingyin Ning ◽  
Hong Su ◽  
Irene Ling Li ◽  
...  
Keyword(s):  
High Performance ◽  
Chemical Potential ◽  
Shape Change ◽  
Optical Switch ◽  
Pulse Amplitude ◽  
Propagation Distance ◽  
Graphene Nanoribbon ◽  
Low Loss ◽  
High Loss ◽  
On Chip

Surface plasmon polaritons (SPPs) have been attracting considerable attention owing to their unique capabilities of manipulating light. However, the intractable dispersion and high loss are two major obstacles for attaining high-performance plasmonic devices. Here, a graphene nanoribbon gap waveguide (GNRGW) is proposed for guiding dispersionless gap SPPs (GSPPs) with deep-subwavelength confinement and low loss. An analytical model is developed to analyze the GSPPs, in which a reflection phase shift is employed to successfully deal with the influence caused by the boundaries of the graphene nanoribbon (GNR). It is demonstrated that a pulse with a 4 μm bandwidth and a 10 nm mode width can propagate in the linear passive system without waveform distortion, which is very robust against the shape change of the GNR. The decrease in the pulse amplitude is only 10% for a propagation distance of 1 μm. Furthermore, an array consisting of several GNRGWs is employed as a multichannel optical switch. When the separation is larger than 40 nm, each channel can be controlled independently by tuning the chemical potential of the corresponding GNR. The proposed GNRGW may raise great interest in studying dispersionless and low-loss nanophotonic devices, with potential applications in the distortionless transmission of nanoscale signals, electro-optic nanocircuits, and high-density on-chip communications.

scholarly journals Self-Healing Router Approach for High-Performance Network-on-Chip

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Self Healing ◽  
On Chip

scholarly journals Facile fabrication of graphene-based high-performance microsupercapacitors operating at high temperature of 150 oC

2021 ◽  
Author(s):  
Viktoriia Mishukova ◽  
Nicolas Boulanger ◽  
Artem Iakunkov ◽  
Szymon Sollami Delekta ◽  
Xiaodong Zhuang ◽  
...  
Keyword(s):  
High Temperature ◽  
Energy Storage ◽  
High Performance ◽  
Electronic Circuits ◽  
Industry Applications ◽  
Facile Fabrication ◽  
On Chip

Many industry applications require electronic circuits and systems to operate at high temperature over 150 oC. Although planar microsupercapacitors (MSCs) have great potential for miniaturized on-chip integrated energy storage components,...

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