Improved Electrical Properties and Thermal Stability of GeON Gate Dielectrics Formed by Plasma Nitridation of Ultrathin Oxides on Ge(100)

2011 ◽  
Vol 470 ◽  
pp. 152-157 ◽  
Author(s):  
Heiji Watanabe ◽  
Katsuhiro Kutsuki ◽  
Iori Hideshima ◽  
Gaku Okamoto ◽  
Takuji Hosoi ◽  
...  

We demonstrated the impact of plasma nitridation on thermally grown GeO2 for the purposes of obtaining high-quality germanium oxynitride (GeON) gate dielectrics. Physical characterizations revealed the formation of a nitrogen-rich surface layer on the ultrathin oxide, while keeping an abrupt GeO2/Ge interface without a transition layer. The thermal stability of the GeON layer was significantly improved over that of the pure oxide. We also found that although the GeO2 layer is vulnerable to air exposure, a nitrogen-rich layer suppresses electrical degradation and provides excellent insulating properties. Consequently, we were able to obtain Ge-MOS capacitors with GeON dielectrics of an equivalent oxide thickness (EOT) as small as 1.7 nm. Minimum interface state density (Dit) values of GeON/Ge structures, i.e., as low as 3 x 1011 cm-2eV-1, were successfully obtained for both the lower and upper halves of the bandgap.

1999 ◽  
Vol 567 ◽  
Author(s):  
G.B. Alers ◽  
L.A. Stirling ◽  
R.B. Vandover ◽  
J.P. Chang ◽  
D.J. Werder ◽  
...  

ABSTRACTGate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.


2018 ◽  
Vol 25 (01) ◽  
pp. 1850043
Author(s):  
A. KORKUT

It is well known that the semiconductor surface is easily oxidized by air-media in time. This work studieds the characterization of Schottky diodes and changes in depletion capacitance, which is caused by air exposure of a group of Cu/n-Si/Al Schottky diodes. First, data for current-voltage and capacitance-voltage were a Ren, and then ideality factor, barrier height, built-in potential ([Formula: see text], donor concentration and Fermi level, interfacial oxide thickness, interface state density were calculated. It is seen that depletion capacitance was calculate; whereafter built-in potential played an important role in Schottky diodes characteristic. Built-in potential directly affects the characteristic of Schottky diodes and a turning point occurs. In case of forward and reverse bias, depletion capacitance versus voltage graphics are matched, but in an opposite direction. In case of forward bias, differential depletion capacitance begins from minus values, it is raised to first [Formula: see text], then reduced to second [Formula: see text] under the minus condition. And it sharply gones up to positive apex, then sharply falls down to near zero, but it takes positive values depending on DC voltage. In case of reverse bias, differential depletion capacitance takes to small positive values. In other respects, we see that depletion characteristics change considerably under DC voltage.


2017 ◽  
Vol 897 ◽  
pp. 335-339
Author(s):  
Zhao Yang Peng ◽  
Yi Yu Wang ◽  
Hua Jun Shen ◽  
Yun Bai ◽  
Yi Dan Tang ◽  
...  

Effect of nitrogen annealing on SiC/SiO2 interface properties was comparatively investigated for SiC MOS capacitors. Interface properties were characterized by normalized parallel conductance and interface state density value, and dielectric strength was evaluated by the electric-field-to-breakdown (Ebd). The results exhibited that both fast and slow states were present at the nitrogen-annealed samples’ parallel conductance characteristics. Thus, we could conclude that nitrogen annealing led to incomplete nitridation of SiC/SiO2 interface. Based on the results, nitridation mechanism was simply analyzed. It seemed that the nitridation process started from near conduction band, extending till to mid-band-gap. Besides, when the samples underwent higher temperature nitrogen annealing, more slow states were converted into fast ones, indicating that higher annealing temperature could lead to more effective nitridation. It was suggested that nitrogen annealing resulted in incomplete nitridation of SiC/SiO2 interface regardless of oxide thickness and that this process was limited to the annealing temperature. The higher the annealing temperature was, the more effective the nitridation effects were.


2018 ◽  
Vol 57 (4S) ◽  
pp. 04FG11
Author(s):  
Nguyen Xuan Truyen ◽  
Noriyuki Taoka ◽  
Akio Ohta ◽  
Katsunori Makihara ◽  
Hisashi Yamada ◽  
...  

1999 ◽  
Vol 567 ◽  
Author(s):  
H. Song ◽  
K. R. Farmer

ABSTRACTUsing a leakage-compensated charge (LCCV) technique to obtain static capacitance-voltage (C-V) curves, we extend the standard high-low C-V method for determining the interface state level density, Dit as a function of energy in the silicon band gap to metal-oxide-silicon capacitors in the direct tunneling regime (oxide thickness ∼<3.5 nm). The LCCV technique yields true static C-V curves for oxides at least as thin as 2.8 nm, where the tunnel leakage current is so high that the usual quasistatic C-V measurement is not possible. As applications of this method, Dit is compared for fresh oxides of different tunnel thickness, and Dit is measured before and after constant voltage stress of a 3.5-nm oxide. The stress results indicate, as in other work on thicker oxides, that interface traps are created during the stress, with peak densities both below and above midgap. This approach is expected to be useful for evaluating both ultra-thin oxides and leaky alternate gate dielectrics.


2013 ◽  
Author(s):  
Jr Morris ◽  
Shardo Robert W. ◽  
Higgins James ◽  
Cook Kim ◽  
Tanner Rhonda ◽  
...  

2014 ◽  
Vol 778-780 ◽  
pp. 631-634 ◽  
Author(s):  
Yoshiyuki Akahane ◽  
Takuo Kano ◽  
Kyosuke Kimura ◽  
Hiroki Komatsu ◽  
Yukimune Watanabe ◽  
...  

A nitride layer was formed on a SiC surface by plasma nitridation using pure nitrogen as the reaction gas at the temperature from 800°C to 1400°C. The surface was characterized by XPS. The XPS measurement showed that an oxinitride layer was formed on the SiC surface by the plasma nitridation. The high process temperature seemed to be effective to activate the niridation reaction. A SiO2film was deposited on the nitridation layer to form SiO2/nitride/SiC structure. The interface state density of the SiO2/nitride/SiC structure was lower than that of the SiO2/SiC structure. This suggested that the nitridation was effective to improve the interface property.


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