A Curvature-Compensated, High Power Supply Rejection CMOS Bandgap Reference for MEMS Micro-Accelerometer

2011 ◽  
Vol 483 ◽  
pp. 481-486 ◽  
Author(s):  
Xiao Wei Liu ◽  
Bing Jun Lv ◽  
Peng Fei Wang ◽  
Liang Yin ◽  
Na Xu
Keyword(s):  
Temperature Coefficient ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Rejection Ratio ◽  
Compensation Technique ◽  
Supply Rejection

The reference is an important part in the accelerometer system. With the development of science and technology, the request of the performance of accelerometers is increasingly higher and the precision of reference directly affects the performance of accelerometers. Therefore, a reference voltage applicable to accelerometers is presented based on the analysis of basic principles of conventional bandgap reference (BGR) in this paper. A high-order curvature compensation technique, which uses a temperature dependent resistor ratio generated by a high poly resistor and a nwell resistor, effectively serves to reduce temperature coefficient of proposed reference voltage circuit and to a large extent improve its performance. To achieve a high power supply rejection ratio (PSRR) over a broad frequency range, a pre-regulator is introduced to remain the supply voltage of the core circuit of BGR relatively independent of the global supply voltage. The proposed circuitry is designed in standard 2.0μm CMOS process. The simulated result shows that the average temperature coefficient is less than 2ppm/°C in the temperature range from -40 to 120°C. The improvement on temperature coefficient (TC) is about 10 times reduction compared to the conventional approach. And the PSR at DC frequency and 1kHz achieves -107 and -71dB respectively at 9.0V supply voltage.

A Sub-1V High Precision CMOS Bandgap Reference

2013 ◽  
Vol 427-429 ◽  
pp. 1097-1100
Author(s):  
Qian Neng Zhou ◽  
Rong Xue ◽  
Hong Juan Li ◽  
Jin Zhao Lin ◽  
Yun Song Li ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Power Supply ◽  
Output Voltage ◽  
Supply Voltage ◽  
Piecewise Linear ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Compensation Technique ◽  
Simulation Results

In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2016 ◽  
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/℃ at range of -10 ℃ to 100 ℃, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 ℃. The chip area is 534 × 695 um^2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals A sub-1V high PSRR OpAmp based β-multiplier CMOS bandgap voltage reference with resistive division

2019 ◽  
Vol 15 (1) ◽  
pp. 155
Author(s):  
Anass SLAMTI ◽  
Youness MEHDAOUI ◽  
Driss CHENOUNI ◽  
Zakia LAKHLIAI
Keyword(s):  
Temperature Coefficient ◽  
Power Supply ◽  
Supply Voltage ◽  
Voltage Source ◽  
Voltage Reference ◽  
Voltage Range ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Bandgap Voltage Reference ◽  
Supply Rejection

<span lang="EN-US">A sub-1V opamp based β-multiplier CMOS bandgap voltage reference (BGVR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed in this paper. A current mode regulator scheme is inserted to isolate the supply voltage of the operational amplifier (opamp) and the supply voltage of the BGVR core from the supply voltage source in order to reduce ripple sensitivity and to achieve a high PSRR. The proposed circuit is designed and simulated in 0.18-μm standard CMOS technology. The proposed voltage reference delivers an output voltage of 634.6mV at 27°C. Tthe measurement temperature coefficient is 22,3ppm/°C over temperature range -40°C to 140°C, power supply rejection ratio is -93dB at 10kHz and -71dB at 1MHz and a line regulation of 104μV/V is achieved over supply voltage range 1.2V to 1.8V. The layout area of the proposed circuit is 0.0337mm<sup>2</sup>. The proposed sub-1V bandgap voltage reference can be used as an internal voltage reference in low power LDO regulators and switching regulators.</span>

An Improved Bandgap Reference with Curvature-Compensated and High Power Supply Rejection

2016 ◽  
Vol 25 (11) ◽  
pp. 1650147 ◽  
Author(s):  
Hongbing Wu ◽  
Hongxia Liu
Keyword(s):  
High Power ◽  
Power Supply ◽  
Low Frequency ◽  
Bandgap Reference ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Resistor String ◽  
Typical Condition ◽  
Active Design ◽  
Supply Rejection

This paper presents a bandgap reference (BGR) with the characteristics of curvature-compensation and high power supply rejection ratio (PSRR). To achieve a better performance, the base current of BJT is injected to a small segment of resistor string to flatten the temperature variation, and a pre-regulator of the power supply is implemented to improve the PSRR. The circuits, designed in 0.18[Formula: see text][Formula: see text]m BCD technology, exhibit an average voltage of 1.212[Formula: see text]V with temperature coefficient of 2.0[Formula: see text]ppm/[Formula: see text] in the range from [Formula: see text] to 110[Formula: see text] at typical condition, and a power supply rejection ratio of [Formula: see text][Formula: see text]dB at low frequency. After 4-bit trimming, Monte Carlo simulation results show that the proposed design gets an accuracy of 0.29%, with a variation of [Formula: see text][Formula: see text]mV. The active design area is 160[Formula: see text][Formula: see text]m, and the power supply current is about 8.2[Formula: see text][Formula: see text]A.

Design of High Power Supply Rejection Ratio Complementary Metal-Oxide-Semiconductor Bandgap Voltage Reference Using Single Node Approach

2019 ◽  
Vol 17 (10) ◽  
pp. 777-783
Author(s):  
Shishu Pal ◽  
Ashutosh Nandi
Keyword(s):  
High Power ◽  
Power Supply ◽  
Circuit Simulation ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Supply Rejection

This paper describes a compact, low voltage and high power supply rejection ratio (PSRR) Bandgap voltage reference circuit by using subthreshold MOSFETs. The proposed reference circuit is implemented using 0.18 μm CMOS technology. The circuit simulation is performed using the Cadence Spectre and Synopsys Hspice. The circuit generates the mean output reference voltage of 164 mV and temperature coefficient of 15.5 ppm/°C when temperature is swept from –40 °C to 120 °C at power supply of 1.2 V. For better PSRR, a feed forward mechanism is used. The proposed design has only single transistor for start-up circuit. The measured settling time for output reference voltage is observed to be less than 4 μs. No filtering capacitor is used to improve the PSRR, which is –97 dB up to 1 MHz and subsequently reduces to –47.5 dB at 158 MHz.

A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC

2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI
Keyword(s):  
High Power ◽  
Power Supply ◽  
Cmos Process ◽  
High Loop ◽  
Wide Range ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Large Output ◽  
Supply Rejection

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.

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