scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2016 ◽  
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/℃ at range of -10 ℃ to 100 ℃, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 ℃. The chip area is 534 × 695 um^2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

A Curvature-Compensated, High Power Supply Rejection CMOS Bandgap Reference for MEMS Micro-Accelerometer

2011 ◽  
Vol 483 ◽  
pp. 481-486 ◽  
Author(s):  
Xiao Wei Liu ◽  
Bing Jun Lv ◽  
Peng Fei Wang ◽  
Liang Yin ◽  
Na Xu
Keyword(s):  
Temperature Coefficient ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Rejection Ratio ◽  
Compensation Technique ◽  
Supply Rejection

The reference is an important part in the accelerometer system. With the development of science and technology, the request of the performance of accelerometers is increasingly higher and the precision of reference directly affects the performance of accelerometers. Therefore, a reference voltage applicable to accelerometers is presented based on the analysis of basic principles of conventional bandgap reference (BGR) in this paper. A high-order curvature compensation technique, which uses a temperature dependent resistor ratio generated by a high poly resistor and a nwell resistor, effectively serves to reduce temperature coefficient of proposed reference voltage circuit and to a large extent improve its performance. To achieve a high power supply rejection ratio (PSRR) over a broad frequency range, a pre-regulator is introduced to remain the supply voltage of the core circuit of BGR relatively independent of the global supply voltage. The proposed circuitry is designed in standard 2.0μm CMOS process. The simulated result shows that the average temperature coefficient is less than 2ppm/°C in the temperature range from -40 to 120°C. The improvement on temperature coefficient (TC) is about 10 times reduction compared to the conventional approach. And the PSR at DC frequency and 1kHz achieves -107 and -71dB respectively at 9.0V supply voltage.

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

2013 ◽  
Vol 660 ◽  
pp. 113-118
Author(s):  
Jhin Fang Huang ◽  
Wen Cheng Lai ◽  
Kun Jie Huang ◽  
Ron Yi Liu
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area ◽  
Low Pass ◽  
Σδ Modulator

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

The Design of Bandgap Reference Based on Empyrean Aether Software

2014 ◽  
Vol 687-691 ◽  
pp. 3489-3493
Author(s):  
Wei Qu ◽  
Li Mei Hou ◽  
Xiao Xin Sun ◽  
Jing Yu Sun ◽  
Liang Yu Li
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
Reference Voltage ◽  
Voltage Source ◽  
Reference Source ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Reference Voltage Source

A high-performance bandgap reference voltage source design method is proposed in this paper, according to the shortcomings of traditional bandgap reference voltage source. This method combined CSMC 0.35μm CMOS process with Aether software technology, enabling to improve the bandgap reference source op amp performance and take into account accuracy and stability of the system. From the experimental results: this bandgap reference voltage source output voltage has changed about 63 mV when the temperature varied from to , and the line regulator is 0.4mV/V when the power supply voltage varied from 3.2V to 3.3V. This system has advantages of high accuracy and good stability.

Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000820-000824 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Wen Cheng Lai ◽  
Yong-Jhen Jiangn
Keyword(s):  
Communication Systems ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Third Order ◽  
Chip Design ◽  
Chip Area ◽  
Rf Receiver ◽  
Front End ◽  
On Chip

An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The measured results of the chip show an input return loss of 20 dB, a conversion gain of 29 dB, a double-side band (DSB) noise figure (NF) of 5 dB, and a third-order intercept point (IIP3) of −24.4 dBm. The on-chip oscillator shows the measured tuning range of 5.17–5.98 GHz and phase noise of −118.5 dBc/Hz at 1 MHz offset from the 5.8 GHz carrier. The proposed receiver front-end is fabricated in a 0.18 μm CMOS process with a power consumption of 27.6 mW from a 1 V supply voltage. The chip area including PADs is 1.75 × 1.2 mm2.

A CMOS Bandgap References Voltage Circuit Using Current Conveyor for Power Management Applications

2013 ◽  
Vol 385-386 ◽  
pp. 1335-1339 ◽  
Author(s):  
Min Chin Lee ◽  
Chi Jing Hu
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Output Resistance ◽  
Operation Temperature ◽  
Resistive Loading ◽  
Chip Size ◽  
Is Design

This paper proposes a low power bandgap reference voltage circuit that provides an output reference voltage close to the bandgap voltage having a low output resistance and allows resistive loading. This proposed circuit is design and implemented using the TSMC 0.18μm 1P6M CMOS process. Simulation and measured results verify that the chip size is with power dissipation about 0.1mW, and the operation temperature range formwith temperature coefficient about . The chip supply voltage can from 1.3 to 1.8V with PSRR about 70 dB, and its output reference voltage can stable on .

Resistorless Frequency Locked On-Chip Oscillator with Proportional-to-Absolute Temperature References

2019 ◽  
Vol 28 (10) ◽  
pp. 1950162 ◽  
Author(s):  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Chip Area ◽  
Frequency Spread ◽  
Temperature Coefficient Of Frequency ◽  
On Chip

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[Formula: see text]m standard CMOS process with an active area of 0.072[Formula: see text]mm2. The temperature coefficient of frequency is 48[Formula: see text]ppm/∘C at best and 82.5[Formula: see text]ppm/∘C on average over [Formula: see text]–70∘C and the frequency spread is 1.43% ([Formula: see text]/[Formula: see text] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[Formula: see text]V to 1[Formula: see text]V and the power consumption is 95[Formula: see text]nW under the supply voltage of 0.65[Formula: see text]V.

A Sub-1V High Precision CMOS Bandgap Reference

2013 ◽  
Vol 427-429 ◽  
pp. 1097-1100
Author(s):  
Qian Neng Zhou ◽  
Rong Xue ◽  
Hong Juan Li ◽  
Jin Zhao Lin ◽  
Yun Song Li ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Power Supply ◽  
Output Voltage ◽  
Supply Voltage ◽  
Piecewise Linear ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Power Supply Voltage ◽  
Compensation Technique ◽  
Simulation Results

In this paper, a low temperature coefficient bandgap voltage (BGR) is designed for A/D converter by adopting piecewise-linear compensation technique. The designed BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the PSRR of the designed BGR achieves-72.51dB, -72.49dB, and-70.58dB at 10Hz, 100Hz and 1kHz respectively. The designed BGR achieve the temperature coefficient of 1.57 ppm/°C when temperature is in the range from-35°C to 125°C. When power supply voltage VDD changes from 1V to 7V, the deviation of the designed BGR output voltage VREF is only 4.465μV.

scholarly journals A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

2017 ◽  
Vol 2017 ◽  
pp. 1-10
Author(s):  
Jinpeng Qiu ◽  
Tong Liu ◽  
Xubin Chen ◽  
Yongheng Shang ◽  
Jiongjiong Mo ◽  
...  
Keyword(s):  
Operational Amplifier ◽  
Supply Voltage ◽  
Bandgap Reference ◽  
Digital To Analog Converter ◽  
Future Design ◽  
Differential Nonlinearity ◽  
Self Bias ◽  
Analog Converter ◽  
Digital To Analog ◽  
Low Offset

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

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