High Throughput SiC Wafer Polishing with Good Surface Morphology

We report SiC wafer polishing study to achieve high throughput with extremely flat, smooth and damageless surface. The polishing consists of three process, wafer grinding, lapping and chemical mechanical polishing (CMP), which are completed in shortest about 200 minutes in total for 2 inch wafer. Specimens of 4H- and 6H-SiC were provided from slicing single crystal as wafers oriented (0001) with 0 or 8 degrees offset angle toward to <112 _ 0>. By the first grinding using a diamond whetstone wheel, we realized flat surface on the wafers with small TTV error of 1 μm in 15 minutes. After second process of lapping, the wafers were finished by CMP using colloidal silica slurry. AFM observation showed not only scratch-free surface but also atomic steps on the wafers after CMP. Rms marks extremely flat value of 0.08 nm in 10 μm square area.

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Effect of Process Parameters on Material Removal Rate in Chemical Mechanical Polishing of 6H-SiC(0001)

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.831 ◽

2008 ◽

Vol 600-603 ◽

pp. 831-834 ◽

Cited By ~ 9

Author(s):

Joon Ho An ◽

Gi Sub Lee ◽

Won Jae Lee ◽

Byoung Chul Shin ◽

Jung Doo Seo ◽

...

Keyword(s):

Material Removal Rate ◽

Chemical Mechanical Polishing ◽

Material Removal ◽

Colloidal Silica ◽

Removal Rate ◽

Mechanical Polishing ◽

Diamond Particles ◽

Average Grain Size ◽

Silica Slurry ◽

Sic Wafer

2inch 6H-SiC (0001) wafers were sliced from the ingot grown by a conventional physical vapor transport (PVT) method using an abrasive multi-wire saw. While sliced SiC wafers lapped by a slurry with 1~9㎛ diamond particles had a mean height (Ra) value of 40nm, wafers after the final mechanical polishing using the slurry of 0.1㎛ diamond particles exhibited Ra of 4Å. In this study, we focused on investigation into the effect of the slurry type of chemical mechanical polishing (CMP) on the material removal rate of SiC materials and the change in surface roughness by adding abrasives and oxidizer to conventional KOH-based colloidal silica slurry. The nano-sized diamond slurry (average grain size of 25nm) added in KOH-based colloidal silica slurry resulted in a material removal rate (MRR) of 0.07mg/hr and the Ra of 1.811Å. The addition of oxidizer (NaOCl) in the nano-size diamond and KOH based colloidal silica slurry was proven to improve the CMP characteristics for SiC wafer, having a MRR of 0.3mg/hr and Ra of 1.087Å.

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High Throughput SiC Wafer Polishing with Good Surface Morphology

Materials Science Forum - Silicon Carbide and Related Materials 2006 ◽

10.4028/0-87849-442-1.753 ◽

2007 ◽

pp. 753-756

Author(s):

Tomohisa Kato ◽

Keisuke Wada ◽

Eiji Hozomi ◽

Hiroyoshi Taniguchi ◽

Tomonori Miura ◽

...

Keyword(s):

Surface Morphology ◽

High Throughput ◽

Good Surface ◽

Wafer Polishing ◽

Sic Wafer

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Colloidal Silica based High Selectivity Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Slurry

MRS Proceedings ◽

10.1557/proc-867-w8.5 ◽

2005 ◽

Vol 867 ◽

Cited By ~ 2

Author(s):

Kyoung-Ho Bu ◽

Brij M. Moudgil

Keyword(s):

Silicon Nitride ◽

Chemical Mechanical Polishing ◽

Colloidal Silica ◽

Sodium Dodecyl ◽

Mechanical Polishing ◽

Wafer Surface ◽

Shallow Trench Isolation ◽

Pattern Size ◽

Trench Isolation ◽

Silica Slurry

AbstractAmong various properties of chemical mechanical polishing (CMP) slurry, selectivity plays a key role in global planarization of high density and small pattern size shallow trench isolation (STI) process. Lack of adequate selectivity can lead to defects such as dishing and erosion. To improve the selectivity of STI CMP process, CMP characteristics of silica and silicon nitride wafer were investigated using colloidal silica slurry as a function of slurry pH. Sodium dodecyl sulfate (SDS), an anionic surfactant, was added to increase the selectivity of the slurry. As a result, selectivity increased from 3 to 25. It was concluded that selective passivation layer formed on silicon nitride wafer surface at acidic slurry pH range was responsible for the observed selectivity increase. Adsorption characteristics of SDS on silica and silicon nitride were measured as a function of slurry pH and concentration of SDS. As indicated by zeta potential behavior under acidic pH conditions, SDS adsorption on silicon nitride was significantly higher han silica due to the electrostatic forces. Significantly higher SDS coating on silicone nitride seems to have resulted in lubrication layer leading to increased polishing selectivity.

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Effect of Recycling Time on Stability of Colloidal Silica Slurry and Removal Rate in Silicon Wafer Polishing

Journal of the Korean Ceramic Society ◽

10.4191/kcers.2007.44.2.098 ◽

2007 ◽

Vol 44 (2) ◽

pp. 98-102 ◽

Cited By ~ 1

Author(s):

Eun-Suck Choi ◽

So-Ik Bae

Keyword(s):

Silicon Wafer ◽

Colloidal Silica ◽

Removal Rate ◽

Wafer Polishing ◽

Silica Slurry

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Development of Lapping and Polishing Technologies of 4H-SiC Wafers for Power Device Applications

Materials Science Forum ◽

10.4028/www.scientific.net/msf.600-603.819 ◽

2008 ◽

Vol 600-603 ◽

pp. 819-822 ◽

Cited By ~ 8

Author(s):

Hirokatsu Yashiro ◽

Tatsuo Fujimoto ◽

Noboru Ohtani ◽

Taizo Hoshino ◽

Masakazu Katsuno ◽

...

Keyword(s):

Colloidal Silica ◽

Wafer Surface ◽

Thickness Variation ◽

Atomic Force ◽

Atomic Force Microscope Observation ◽

Device Applications ◽

Total Thickness Variation ◽

Silica Slurry ◽

Sic Wafer ◽

Chemical Polishing Process

The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.

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Effect of Alkaline Agent in Colloidal Silica Slurry for Polycrystalline Silicon Chemical Mechanical Polishing

Japanese Journal of Applied Physics ◽

10.1143/jjap.46.5089 ◽

2007 ◽

Vol 46 (8A) ◽

pp. 5089-5094 ◽

Cited By ~ 18

Author(s):

Myung-Yoon Lee ◽

Hyun-Goo Kang ◽

Manabu Kanemoto ◽

Ungyu Paik ◽

Jea-Gun Park

Keyword(s):

Chemical Mechanical Polishing ◽

Polycrystalline Silicon ◽

Colloidal Silica ◽

Mechanical Polishing ◽

Alkaline Agent ◽

Silica Slurry

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Chemical mechanical polishing (CMP) of on-axis Si-face 6H-SiC wafer for obtaining atomically flat defect-free surface

Journal of Materials Science Materials in Electronics ◽

10.1007/s10854-013-1519-1 ◽

2013 ◽

Vol 24 (12) ◽

pp. 5040-5047 ◽

Cited By ~ 15

Author(s):

Guoshun Pan ◽

Yan Zhou ◽

Guihai Luo ◽

Xiaolei Shi ◽

Chunli Zou ◽

...

Keyword(s):

Free Surface ◽

Chemical Mechanical Polishing ◽

Mechanical Polishing ◽

Sic Wafer ◽

Atomically Flat

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The Surface Damage in SiO2 Caused by Chemical Mechanical Polishing on Ic-60 Pads

MRS Proceedings ◽

10.1557/proc-337-157 ◽

1994 ◽

Vol 337 ◽

Cited By ~ 2

Author(s):

Shyam Murarka ◽

Sen-Hou Ko ◽

Minoru Tomozawa ◽

Pei-Jun Ding ◽

William A. Lanford

Keyword(s):

Electrical Properties ◽

Nuclear Reaction ◽

Chemical Mechanical Polishing ◽

Colloidal Silica ◽

Surface Damage ◽

Mechanical Polishing ◽

Interlayer Dielectric ◽

Silicon Devices ◽

Thermal Oxide ◽

Silica Slurry

ABSTRACTChemical Mechanical polishing (CMP) is a useful technique for achieving global planarization in the ICs. The CMP of oxide has been used and studied for decades. Only recently the technique has been employed for planarizing the interlayer dielectric (ILD) on the silicon devices circuits. The effect of such polishing on the performance of the ILD has been the concern. This paper examines the attempts on defining the damage caused by CMP and its effect on the electrical properties after polished SiO2 wafers. In this investigation the PECVD and thermal oxide films were polished in the colloidal silica slurry on IC 60 pad. The polished oxide were then studied using I-V and nuclear reaction technique. The results show a surface damage which extends to about 800 Å in the polished oxide. The changes occurring in the concentration of hydrogenous species at the surface of SiO2 as determined by nuclear reaction technique will also be presented. It is shown that due to CMP as-deposited CVD SiO2 films loose water from surface regions whereas well annealed or dry oxides gain water at the surface. The results will be discussed and mechanisms will be presented to explain electrical results.

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