14.6 mΩcm2 3.3 kV DIMOSFET on 4H-SiC (000-1)

2014 ◽  
Vol 778-780 ◽  
pp. 935-938 ◽  
Author(s):  
Hiroshi Kono ◽  
Masaru Furukawa ◽  
Keiko Ariyoshi ◽  
Takuma Suzuki ◽  
Yasunori Tanaka ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Current Spread ◽  
Blocking Voltage

Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2011 ◽  
Vol 679-680 ◽  
pp. 607-612 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Kazuto Takao ◽  
Masaru Furukawa ◽  
Makoto Mizukami ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitor ◽  
Time Dependent Dielectric Breakdown ◽  
Blocking Voltage ◽  
Switching Characteristics

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

scholarly journals Effects of Doping Concentration on Device Performance of GaN-based Nano-regime MOSFETs

2017 ◽  
Vol 16 (1) ◽  
pp. 69-74
Author(s):  
Md Iktiham Bin Taher ◽  
Md. Tanvir Hasan
Keyword(s):  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Gate Length ◽  
Drain Voltage ◽  
Switching Device ◽  
Device Applications

Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are promising for switching device applications. The doping of n- and p-layers is varied to evaluate the figure of merits of proposed devices with a gate length of 10 nm. Devices are switched from OFF-state (gate voltage, VGS = 0 V) to ON-state (VGS = 1 V) for a fixed drain voltage, VDS = 0.75 V. The device with channel doping of 1×1016 cm-3 and source/drain (S/D) of 1×1020 cm-3 shows good device performance due to better control of gate over channel. The ON-current (ION), OFF-current (IOFF), subthreshold swing (SS), drain induce barrier lowering (DIBL), and delay time are found to be 6.85 mA/μm, 5.15×10-7 A/μm, 87.8 mV/decade, and 100.5 mV/V, 0.035 ps, respectively. These results indicate that GaN-based MOSFETs are very suitable for the logic switching application in nanoscale regime.

scholarly journals The gamma-ray irradiation sensitivity and dosimetric information instability of RADFET dosimeter

2013 ◽  
Vol 28 (4) ◽  
pp. 415-421 ◽  
Author(s):  
Milic Pejovic
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Room Temperature ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Gamma Ray Irradiation

The gamma-ray irradiation sensitivity to radiation dose range from 0.5 Gy to 5 Gy and post-irradiation annealing at room and elevated temperatures have been studied for p-channel metal-oxide-semiconductor field effect transistors (also known as radiation sensitive field effect transistors or pMOS dosimeters) with gate oxide thicknesses of 400 nm and 1 mm. The gate biases during the irradiation were 0 and 5 V and 5 V during the annealing. The radiation and the post-irradiation sensitivity were followed by measuring the threshold voltage shift, which was determined by using transfer characteristics in saturation and reader circuit characteristics. The dependence of threshold voltage shift DVT on absorbed radiation dose D and annealing time was assessed. The results show that there is a linear dependence between DVT and D during irradiation, so that the sensitivity can be defined as DVT/D for the investigated dose interval. The annealing of irradiated metal-oxide-semiconductor field effect transistors at different temperatures ranging from room temperature up to 150?C was performed to monitor the dosimetric information loss. The results indicated that the dosimeters information is saved up to 600 hours at room temperature, whereas the annealing at 150?C leads to the complete loss of dosimetric information in the same period of time. The mechanisms responsible for the threshold voltage shift during the irradiation and the later annealing have been discussed also.

High-temperature modeling and characterization of 6H silicon carbide metal-oxide-semiconductor field-effect transistors

2005 ◽  
Vol 97 (4) ◽  
pp. 046106 ◽  
Author(s):  
Stephen K. Powell ◽  
Neil Goldsman ◽  
Aivars Lelis ◽  
James M. McGarrity ◽  
Flynn B. McLean
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Temperature Modeling

Silicon Carbide Power Field-Effect Transistors

MRS Bulletin ◽  
2005 ◽  
Vol 30 (4) ◽  
pp. 293-298 ◽  
Author(s):  
Jian H. Zhao
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Field Effect ◽  
Recent Progress ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
High Power Density ◽  
Advantages And Disadvantages ◽  
Power Switches

AbstractSilicon carbide power field-effect transistors, including power vertical-junction FETs (VJFETs) and metal oxide semiconductor FETs (MOSFETs), are unipolar power switches that have been investigated for high-temperature and high-power-density applications. Recent progress and results will be reviewed for different device designs such as normally-OFF and normally-ON VJFETs, double-implanted MOSFETs, and U-shaped-channel MOSFETs. The advantages and disadvantages of SiC VJFETs and MOSFETs will be discussed. Remaining challenges will be identified.

Observation of Deep Level Centers in 4H and 6H Silicon Carbide Metal Oxide Semiconductor Field Effect Transistors

2005 ◽  
Vol 483-485 ◽  
pp. 593-596 ◽  
Author(s):  
David J. Meyer ◽  
Morgen S. Dautrich ◽  
Patrick M. Lenahan ◽  
Aivars J. Lelis
Keyword(s):  
Silicon Carbide ◽  
Electron Spin Resonance ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Deep Level ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spin Resonance ◽  
Trapping Centers

Utilizing an very sensitive electron spin resonance (ESR) technique, spin dependent recombination (SDR) we have identified interface and near interface trapping centers in 4H and 6H SiC/SiO2 metal oxide semiconductor field effect transistors (MOSFETs). We extend our group’s earlier observations on 6H devices to the more technologically important 4H system and find that several centers can play important roles in limiting the performance of SiC based MOSFETs.

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