Underfill Induced Tensile Strain Ratcheting and its Effect on Flip Chip Solder Bump Fatigue

The effects of low Tg underfill material on the reliability of high-Pb first level interconnects were assessed through elastic-plastic finite element modeling and inspection of failure sites at the first-level interconnect. Temperature-dependent changes in specific underfill parameters (elastic modulus and coefficient of thermal expansion) induced a primary tensile stress within the solder bump. The presence and magnitude of this tensile stress were highly dependent upon the maximum and minimum temperature of exposure. Under certain specific thermal conditions, a form of tensile ratcheting was identified through finite element modeling. The application of tensile stress was found to induce a change in degradation behavior and rates relative to the nominal shear stress state (see Figure). This effectively eliminated distance-to-neutral point as a predictor of first-level interconnects performance and required the development of new models to predict solder bump behavior. A discussion on this transformation in stress states and the potential influence on changes in part qualification procedures are provided.

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Stress-strain curves of flip-chip solder balls based on finite-element modeling of thermal displacements measured by electronic speckle pattern interferometry

Journal of Electronic Materials ◽

10.1007/s11664-003-0030-5 ◽

2003 ◽

Vol 32 (11) ◽

pp. 1322-1329 ◽

Cited By ~ 5

Author(s):

Baik-Woo Lee ◽

Ju-Young Kim ◽

Dongil Kwon

Keyword(s):

Finite Element ◽

Finite Element Modeling ◽

Flip Chip ◽

Speckle Pattern ◽

Electronic Speckle Pattern Interferometry ◽

Stress Strain ◽

Element Modeling ◽

Solder Balls ◽

Thermal Displacements

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Underfill Assessments and Validations for Low-k FCBGA

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology ◽

10.1115/imece2006-15432 ◽

2006 ◽

Author(s):

Nicholas Kao ◽

Jeng Yuan Lai ◽

Jase Jiang ◽

Yu Po Wang ◽

C. S. Hsiao

Keyword(s):

Finite Element ◽

High Speed ◽

Flip Chip ◽

Failure Modes ◽

Solder Bump ◽

Material Selection ◽

Coefficient Of Thermal Expansion ◽

Electrical Performance ◽

Low K ◽

Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

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Coupled phase field and finite element modeling of void evolution and physical property change of micro flip-chip solder joints under electromigration and elastic stress field

2017 18th International Conference on Electronic Packaging Technology (ICEPT) ◽

10.1109/icept.2017.8046749 ◽

2017 ◽

Author(s):

Shui-Bao Liang ◽

Chang-Bo Ke ◽

Min-Bo Zhou ◽

Xin-Ping Zhang

Keyword(s):

Finite Element ◽

Stress Field ◽

Finite Element Modeling ◽

Phase Field ◽

Flip Chip ◽

Elastic Stress ◽

Physical Property ◽

Property Change ◽

Element Modeling ◽

Void Evolution

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Development of Integrated Process-Ageing Modeling Methodology for Flip Chip on Flex Interconnections With Non-Conductive Adhesives

Advances in Electronic Packaging, Parts A, B, and C ◽

10.1115/ipack2005-73020 ◽

2005 ◽

Cited By ~ 1

Author(s):

Xiaowu Zhang ◽

E. H. Wong ◽

Ranjan Rajoo ◽

Mahadevan K. Iyer ◽

J. F. J. M. Caers ◽

...

Keyword(s):

Finite Element ◽

Finite Element Modeling ◽

Mechanical Stress ◽

Flip Chip ◽

Process Condition ◽

Integrated Process ◽

Conductive Adhesives ◽

Element Modeling ◽

Ageing Test ◽

Modeling Methodology

This paper presents a comprehensive methodology to model the static temperature-humidity (TH) ageing test (85°C/85%RH over 1000 hours) of flip chip on flex interconnections with non-conductive adhesives (NCAs). Nonconductive adhesives, being a special form of conductive adhesives, are chosen, as they allow bringing the pitch further down. The methodology combines experimental techniques for material characterization, finite element modeling (FEM) and model validation. A non-conductive adhesive (NCA) has been characterized using several techniques. The thermomechanical properties and the moisture properties were obtained for the NCA. A temperature dependent viscoelastic constitutive model was also obtained for the NCA. The viscoelastic model was defined by the Prony series expansion. The shift factor was approximated by the Williams-Landel-Ferry (WLF) equation. Finite element modeling has been performed to analyze the flip chip interconnects on flex with the NCA under process condition and reliability ageing conditions. The viscoelastic constitutive relation has been used to model the NCA in ageing modeling. An integrated process-ageing modeling methodology has been developed to combine the thermo-mechanical stress and hygro-mechanical stress, followed by stress relaxation analysis. To verify the finite element models, the static TH ageing test (85°C/85%RH) were also performed. The contact resistance was monitored with high measuring resolution during the accelerated test. The simulation results are good agreement with the experimental results. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters and good reliability performances.

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