Underfill Assessments and Validations for Low-k FCBGA

2006 ◽  
Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao
Keyword(s):  
Finite Element ◽  
High Speed ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Performance ◽  
Low K ◽  
Underfill Material

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Effects of Low CTE Materials on Thermal Deformation of Organic Substrates in Flip Chip Package Application

2015 ◽  
Author(s):  
Hiroyuki Mori ◽  
Sayuri Kohara ◽  
Keishi Okamoto ◽  
Hirokazu Noma ◽  
Kazushige Toriyama
Keyword(s):  
Finite Element ◽  
Thermal Deformation ◽  
Flip Chip ◽  
Material Selection ◽  
Coefficient Of Thermal Expansion ◽  
Layer Structure ◽  
Surface Profile ◽  
Organic Substrates ◽  
Convex Shape ◽  
Typical Application

Coefficient of thermal expansion (CTE) characteristic of organic materials for substrates in flip chip package application demanded by semiconductor package requirements is becoming lower than ever. In general, height restrictions are imposed on package-on-package (PoP) devices in mobile applications. One should hence establish a tight budget on the height variation in manufacturing of the devices. Given such background, a lowering of the CTE characteristic of package substrates is an attractive solution for reducing package deformation upon manufacturing, since it contributes to minimize CTE mismatch of the substrates with silicon chips. In large-die flip chip applications such as high-end processors, a lower CTE substrate can mitigate mechanical stress not only on low-k layers in back end of the line (BEOL) underneath the chip bumps, but also on underfill layers during thermal cycling. Therefore an introduction of lower CTE materials in organic substrates is becoming essential for future applications of electronic devices. In this paper, thermal deformation behaviors of organic substrates associated with lowering of the CTEs of their constituent materials are analyzed by finite element analysis (FEA). The analyses are done on a 3-2-3 build-up layer structure substrate in order to focus onto typical application specific integrated circuit (ASIC) products. A finite element model for a test substrate is constructed by a method in which the substrate is divided into sections according to its circuitry patterns so that the lateral inhomogeneity of mechanical property is taken into account. The finite element analyses using the model showed that the package warpage decreases with lowering of the effective CTE of the substrate, but the warpage of the substrate itself increases and its surface profile changes from a concave shape to a convex shape. The analysis result of substrate warpage variation with the build-up material’s CTE showed that the selection of build-up materials with appropriate material properties can contribute to reduce the substrate warpage. The analysis also showed that the adverse impact to the substrate’s CTE reduction by such material selection is limited.

Underfill Induced Tensile Strain Ratcheting and its Effect on Flip Chip Solder Bump Fatigue

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000737-000758 ◽  
Author(s):  
Craig D. Hillman ◽  
Randy Schueller ◽  
Greg Caswell
Keyword(s):  
Finite Element ◽  
Tensile Stress ◽  
Finite Element Modeling ◽  
Flip Chip ◽  
Solder Bump ◽  
Coefficient Of Thermal Expansion ◽  
Thermal Conditions ◽  
Temperature Dependent ◽  
Element Modeling ◽  
Stress States

The effects of low Tg underfill material on the reliability of high-Pb first level interconnects were assessed through elastic-plastic finite element modeling and inspection of failure sites at the first-level interconnect. Temperature-dependent changes in specific underfill parameters (elastic modulus and coefficient of thermal expansion) induced a primary tensile stress within the solder bump. The presence and magnitude of this tensile stress were highly dependent upon the maximum and minimum temperature of exposure. Under certain specific thermal conditions, a form of tensile ratcheting was identified through finite element modeling. The application of tensile stress was found to induce a change in degradation behavior and rates relative to the nominal shear stress state (see Figure). This effectively eliminated distance-to-neutral point as a predictor of first-level interconnects performance and required the development of new models to predict solder bump behavior. A discussion on this transformation in stress states and the potential influence on changes in part qualification procedures are provided.

Solder Joint Reliability in Underfilled Flip Chip Package With a Consideration of Chip-Package-Interaction (CPI)

2011 ◽  
Author(s):  
Jae B. Kwak ◽  
Da Yu ◽  
Tung T. Nguyen ◽  
Seungbae Park
Keyword(s):  
Mechanical Behavior ◽  
Flip Chip ◽  
Thermal Loading ◽  
Solder Bump ◽  
Image Correlation ◽  
Specimen Preparation ◽  
Solder Bumps ◽  
Low K ◽  
Underfill Material ◽  
Dic Technique

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which may compromise the life of flipchip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. As a specimen preparation for DIC technique, a flip-chip specimen was cross-sectioned before a manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

scholarly journals Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 295
Author(s):  
Pao-Hsiung Wang ◽  
Yu-Wei Huang ◽  
Kuo-Ning Chiang
Keyword(s):  
Finite Element ◽  
Thermal Cycling ◽  
Glass Substrate ◽  
High Speed ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Design Parameters ◽  
Time To Failure ◽  
Wafer Level ◽  
Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Failure Prediction of Flip Chip Packages Using Finite Element Technique

2002 ◽  
Author(s):  
Abm Hasan ◽  
H. Mahfuz ◽  
M. Saha ◽  
S. Jeelani
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Thermal Loading ◽  
Failure Modes ◽  
Element Model ◽  
Thermally Induced ◽  
Operational Life ◽  
Flip Chip Assembly ◽  
The Individual ◽  
Element Technique

Flip-chip electronic package undergoes thermal loading during its curing process and operational life. Due to the thermal expansion coefficient (CTE) mismatch of various components, the flip-chip assembly experiences various types of thermally induced stresses and strains. Experimental measurement of these stresses and strains is extremely tedious and rigorous due to the physical limitations in the dimensions of the flip-chip assembly. While experiments provide accurate assessment of stresses and strains at certain locations, a parallel finite element (FE) analysis and analytical study can complementarily determine the displacement, strain and stress fields over the entire region of the flip-chip assembly. Such combination of experimental, finite element and analytical studies are ideal to yield a successful stress analysis of the flip-chip assembly under the various loading conditions. In this study, a two-dimensional finite element model of the flip-chip consisting of the silicon chip, underfill, solder ball, copper pad, solder mask and substrate has been developed. Various stress components under thermal loading condition ranging from −40°C to 150°C have been determined using both the finite element and analytical methods. Stresses such as (σ11, σ12, ε12 etc. are extracted and analyzed for the individual components as well as the entire assembly, and the weakest positions of the flip-chip have been discovered. Detailed description of FE modeling is presented and the different failure modes of chip assembly are discussed.

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