Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
Latest Publications


TOTAL DOCUMENTS

68
(FIVE YEARS 0)

H-INDEX

3
(FIVE YEARS 0)

Published By ASMEDC

0791847691

Author(s):  
Zhengfang Qian

This paper presents a damage mechanics-based methodology for the progressive damage and virtual qualification of advanced electronic packages such as BGAs, DCAs, CSPs, and Flip-chips. The key technique is to implement the material nonlinearity into commercially available software tools. A unified viscoplastic constitutive framework with the damage evolution and failure criteria has been successfully implemented into the ABAQUS® code to model time-rate-temperature dependent material properties. The framework has been successfully applied to solder alloys, polymer films, and underfill encapsulants. The mathematical structure and numerical algorithm development of the unified constitutive framework as well as the key implementation techniques for commercial FEA codes have been summarized in this paper. Both crack initiation and propagation of a solder joint with damage evolution under mechanical cyclic loading have been demonstrated. Virtual simulations of TSOP component failure under mechanical cyclic loading and BGA package under thermal cyclic loading have also been presented.


Author(s):  
Mohammad Faizan ◽  
Guo-X. Wang

Soldering has become an indispensable joining process in the electronic packaging industry. The industry is aiming for the use of environment friendly lead-free solders. All the lead-free solders are high tin-containing alloys. During the soldering process, an intense interaction of metallization on PCB and tin from the solder occurs at the metallization/solder interface. Intermetallic compound (IMC) is formed at the interface and subsequently PCB bond-metal (substrate) is dissolved into the molten solder. In the present study the terms bond-metal and substrate will be used interchangeably and the term 'substrate' refers to the top layer of the PCB which comes in contact with the molten solder during soldering reaction. Thickness of the intermetallic phase formed at the joint interface and amount of substrate lost is critical in achieving reliable solder joints. During the wet phase of soldering process, the IMC does not grow as layered structure; rather it takes the shape of scallops. The growth of scalloped IMC during the solder/substrate interaction entails complicated physics. Understanding of the actual kinetics involved in the formation of IMC phase is important in controlling the process to achieve desired results. This paper presents theoretical analysis of the kinetics involved in the formation of the scalloped intermetallic phase. The intermetallic phase growth is experimentally investigated to support the underlying kinetics of the process. Numerical model has been suggested to translate the physics of the process. The model is based on the basic mass diffusion equations and can predict the substrate dissolution and IMC thickness as a function of soldering time.


Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.


Author(s):  
Keng H. Hsu ◽  
Placid M. Ferreira ◽  
Nicholas Fang

Among the subtractive fabrication techniques nanoimprint lithography followed by metal etching processes3,4,5 provides features with size down to tens of nanometers6,7. With the aid of high strength tool, the resolution of electrochemical machining (ECM) has been pushed to sub-hundred nanometer regime4. As much as the high resolution it is capable of, nanoimprint lithography followed by metal etching processes bears the multi-step, complex lithography processes that require stringent process environment control and high-cost equipments. Similarly, the pattern dimension fidelity and pattern geometry of the transferred feature is limited by the current density distribution in the liquid-state electrolyte and its physical properties. Effort has been on developing patterning techniques and logic devices that are based on the ionic mass transport property in solid electrolytes. A quantized conductance atomic switch that operates at 1MHz with 0.6V of driving potential has been developed wherein silver mobile atoms bridges and opens the tunneling gap between Pt and silver sulfide wires when driven by a gate potential8. Nanopatterning techniques utilizing local metal cluster deposition and dissolution have also been developed to achieve sub-hundred nanometer line writing and dot deposition with scanning probe microscopy9,10,11. Here we present a novel solid state ionic subtractive stamping technique which provides nanoscale patterning of metallic features with high resolution. Developed based upon a single-step electrochemical material dissolution process in ambient conditions, this technique offers high throughput and high fidelity in metal pattern transfer at nanoscale, as well as the flexibility to be used for various kinds of metals and to be integrated with other nano-fabrication techniques for applications such as chemical sensors and photonic structures. Shown in Figure 1 is a model of ionic migration of silver species in a solid-state ionic conductor, silver sulfide. When subjected to an electric field applied across a silver-silver sulfide interface through anode and cathode attached to them respectively, in achieving the equilibrium of the electrochemical potential of silver atoms in the silver substrate and that in silver sulfide, silver atoms in the substrate oxidize into mobile ions and electrons. These mobilized silver ions then move freely from the interface through the conduction channels in the silver sulfide bulk towards the cathode. Upon receiving electrons when reaching cathode, silver ions reduce back to atoms and deposit on the interface between the cathode and Ag2S. The oxidation at the interface between anode and Ag2S is an ideal tool for surface micromachining in that mass transport only occurs at the portion of the surfaces of anode where actual physical contact exists, making it an ideal tool for pattern transfer. In our preliminary experiments, silver sulfide and silver substrate were chosen and stamping apparatus was built to perform solid state ionic subtractive stamping. Stamping was performed with the chronoamperometry operation mode of the Potentiostat for chosen potentials. Stampings were also run with a fixed potential of 0.3 V but different lengths of time for stamping rate analysis. Shown in figure 2 are the SEM images of the silver sulfide stamp and the produced silver feature. The lateral resolution achieved is 120nm for line width. Shown in figure 3 are the stamping depths measured at different time steps of a stamping process and the calculated stamping rates at different time steps. The silver removal rate throughout the stamping process is found to remain the same. The constant stamping rate suggests constant ionic conduction which means constant ionic conductivity-the ionic conductivity of silver sulfide remains constant irrespective of silver concentration change, or the composition of the silver sulfide stamp. This is in good agreement with Hebb and Wagner12,13 in their electrochemical measurements of silver sulfide which states that ionic conductivity of silver sulfide is almost independent of composition, given the structure of β-form silver sulfide is quite open and the considerable freedom in the disposition of silver ions. The rough surface of the generated features seen in figure 2 is thought to be due to the small depth of the pattern on the silver sulfide stamp which causes undesirable etch of silver and pulling of silver grains; the characterization and optimization of it is currently being investigated. To conclude, we have demonstrated a unique technique to pattern metal with sub-micron resolution in a high-throughput stamping process. The process is a solid-state, room temperature process that is highly compatible with a large variety of process technologies. In our initial attempt, a lateral resolution of 120nm is achieved.


Author(s):  
J. Varghese ◽  
A. Dasgupta

This paper characterizes the fatigue failure envelopes for solder damage in Printed Wiring Assemblies (PWAs) subjected to dynamic loading. An empirical, rate-dependent, power-law durability model, motivated by mechanistic considerations, is used to characterize the failure envelopes in terms of PWA flexural strain and strain rate. Explicit nonlinear finite element analysis (FEA) is used to make the damage constants independent of the specimen geometry and characterize the durability in terms of the ratio of solder plastic strain to its failure strain. A case study, using a simple PWA specimen containing a single area array component, is presented to demonstrate the proposed approach.


Author(s):  
Q. Huang ◽  
C. M. Lilley ◽  
K. M. Paing

Gold nanowires were patterned with e-beam lithography and fabricated with a gold film deposited by e-beam evaporation. Carbon and oxygen contaminants were found to be present mostly on the gold surface with x-ray photoelectron spectroscopy. Slight carbon contamination was indicated through the film thickness. Dimensions of the nanowires were measured with scanning electron microscopy, and the resistance of the wires was measured with a 2-probe stage at a low vacuum. Non-linear current-voltage curves were obtained, which was attributed to Joule heating. Further analysis, by restricting the bias voltage in a small range and negligible Joule heating, suggests that surface contamination can significantly affect the resistivity measurements of gold nanowires.


Author(s):  
Mohd F. Abdulhamid ◽  
Cemal Basaran ◽  
Douglas C. Hopkins

The study of thermomigration on Sn-Ag-Cu solder sphere subjected to a high thermal gradient of 1100°C/cm is presented. After 286 hours, the hot end showed a thin and flat intermetallic compound (IMC) while the cold side showed a scallop-like Cu6Sn5 IMC. Small voids can be seen within the Cu6Sn5 IMC after 712 hours on the cold side, while the IMC on the opposite side showed no observable changes.


Author(s):  
Felix Bruno ◽  
Purushothaman Damodaran ◽  
Krishnaswami Srihari ◽  
Guhan Subbarayan

The electronics manufacturing industry is gradually migrating towards to a lead-free environment. During this transition, there will be a period where lead-free materials will need to coexist with those containing lead on the same assembly. The use of tin-lead solder with lead-free parts and lead-free solder with components containing lead can hardly be avoided. If it can be shown that lead-free Ball Grid Arrays (BGAs) can be successfully assembled with tin-lead solder while concurrently obtaining more than adequate solder joint reliability, then the Original Equipment Manufacturers (OEMs) will accept lead-free components regardless of the attachment process or material used. Consequently, the Electronics Manufacturing Service (EMS) providers need not carry both the leaded and the unleaded version of a component. Solder voids are the holes and recesses that occur in the joints. Some say the presence of voids is expected to affect the mechanical properties of a joint and reduce strength, ductility, creep, and fatigue life. Some believe that it may slow down crack propagation by forcing a re-initiation of the crack. Consequently, it has the ability to stop a crack. The primary objective of this research effort is to develop a robust process for mixed alloy assemblies such that the occurrence of voids is minimized. Since there is no recipe currently available for mixed alloy assemblies, this research will study and 'optimize' each assembly process step. The difference between the melting points of lead-free (217°C) and tin-lead (183°C) solder alloys is the most important constraint in a mixed alloy assembly. The effect of voids on solder joint reliability in tin-lead assembly is well documented. However, its effect on lead-free and mixed alloy assemblies has not received due attention. The secondary objective of this endeavor is to determine the percentage of voids observed in mixed alloy assemblies and compare the results to both tin-lead and lead-free assemblies. The effect of surface finish, solder volume, reflow profile parameters, and component pitch on the formation of voids is studied across different assemblies. A designed experiments approach is followed to develop a robust process window for mixed alloy assemblies. Reliability studies are also conducted to understand the effect of voids on solder joint failures when subjected to accelerated testing conditions.


Author(s):  
Jiantao Zheng ◽  
Suresh K. Sitaraman

Characterization of interfacial fracture parameters for nano-scale thin films continues to be challenging due to the difficulties associated with preparing samples, fixturing and loading the samples, and extracting and analyzing the experimental data. In this paper, we propose a stress-engineered superlayer test method that can be used to measure the interfacial fracture parameters of nano-scale (as well as micro-scale) thin films without the need for loading fixtures. The proposed test employs the residual stress in sputter-deposited metals to provide the energy for interfacial crack propagation. The innovative aspect of the test is the use of an etchable release layer that is deposited between the two interfacial materials of interest. The release layer is designed such that the available energy for interfacial crack propagation will continue to decrease as the crack propagates, and at the location where the crack ceases to propagate, the available energy for crack propagation will be the critical energy for crack propagation or the interfacial fracture toughness. The proposed test method has been successfully used to characterize Ti thin film on Si substrate.


Author(s):  
Jaime Villafuerte

In order to take advantage of the global economy, manufacturing companies have developed a complex and an extended supply chain which includes manufacturing components or parts in LCCs (low-cost countries) and shipping them to factories near to their consumer market for final assembly, customization and distribution. These activities involve several different organizations that follow widely different approaches in logistical management. In order to sustain the long shipment distances in different geographic regions, (i.e. China-Mexico-US-Europe), handling & environmental conditions & shipping modes (Air vs Ground vs Sea); suitable, flexible and economical packaging solutions are required. This flow of semi-finished goods usually requires packaging materials such as carriers (i.e. wooden pallets) and moisture inhibitors (i.e. desiccants) to protect the goods. Competitive pressures, environmental consciousness, customer awareness and legislative requirements have driven manufacturers to review business practices and redesign solutions that are environmentally friendly, as well as help reduce costs in the long run. The author of this paper will present an experience where "non-traditional" packaging is used as an economical and environmental friendly solution to globally transport goods between multiple facilities.


Sign in / Sign up

Export Citation Format

Share Document