Low Cost, High Reliability WLCSP for Higher Pin Counts

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002336-002359
Author(s):  
Tony Curtis ◽  
Senthil Sivaswamy ◽  
Ronnie Yazzie ◽  
David Lawhead ◽  
Theodore G. Tessier
Keyword(s):  
Test Performance ◽  
High Reliability ◽  
Low Cost ◽  
Cycling Performance ◽  
Wafer Level ◽  
End User ◽  
The Past ◽  
Board Level ◽  
Board Level Reliability ◽  
Proper Balance

The proliferation of Wafer Level Chip Scale Packages (WLCSPs) in portable handheld products has occurred due to the minimalist form factor, high reliability and low cost packaging that they afford. As the demand for WLCSPs has grown exponentially in recent years, the industry has also been coping concurrently with the technical challenges associated with increasing array sizes and more demanding end user reliability requirements. Since handsets are inherently prone to being dropped, they are particularly susceptible to this type of component failure though striking a proper balance of mechanical robustness and thermal cycling performance has remained an ongoing industry goal. Similar to other packages, WLCSPs have transitioned over the past decade from lead-based solder alloys to Lead Free (LF) solders. LF solder connections are especially susceptible to brittle fracture and can result in variations in drop test performance from one bump structure to the next. This paper will provide an overview of process and material add-on strategies that have been shown to considerably improve mechanical robustness for bump structures or bumping applications that are inherently less robust than others. Such supplemental improvements can result in passing Board Level Reliability qualification requirements which may otherwise be elusive or have limited levels of reliability reproducibility.

High Reliability Fine Pitch WLCSP for High Pin Count Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001894-001907
Author(s):  
David Lawhead ◽  
Ronnie Yazzie ◽  
Tony Curtis ◽  
Guy Burgess ◽  
Ted Tessier
Keyword(s):  
Silver Content ◽  
High Reliability ◽  
Electrical Performance ◽  
Thermal Testing ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Industry Standard ◽  
Fine Pitch ◽  
Board Level ◽  
Board Level Reliability

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements. This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.

ChipletT, A Cost-Effective, High Reliability, Embedded Die Fan-Out Package Based on Multilayer Flex Laminate with Enhanced Thermal Performance

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-32
Author(s):  
Senthil Sivaswamy ◽  
Theodore (Ted) G. Tessier ◽  
Tony Curtis ◽  
David Clark ◽  
Kazuhisa Itoi ◽  
...  
Keyword(s):  
Thermal Performance ◽  
High Reliability ◽  
Low Cost ◽  
Cost Effective ◽  
Polymer Processing ◽  
Wafer Level ◽  
Component Level ◽  
Novel Approach ◽  
Reliability Performance ◽  
Board Level

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

High Reliability and High Throughput Ball Bumping Process Solution – Solder Joint Encapsulant Adhesives

2017 ◽  
Vol 2017 (1) ◽  
pp. 000001-000007
Author(s):  
Mary Liu ◽  
Wusheng Yin
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Test Performance ◽  
High Reliability ◽  
Cycling Performance ◽  
Bonding Process ◽  
Assembly Process ◽  
Electronic Industry ◽  
Ball Size ◽  
Board Level

Abstract The miniaturization of microchips is always driving force for revolution and innovation in the electronic industry. When the pitch of bumps is getting smaller and smaller the ball size has to be gradually reduced. However the reliability of smaller ball size is getting weaker and weaker, so some traditional methods such as capillary underfilling, corner bonding and edge bonding process have been being implemented in board level assembly process to enhance drop and thermal cycling performance. These traditional processes have been increasingly considered to be bottleneck for further miniaturization because the completion of these processes demands more space. So the interest of eliminating these processes has been increased. To meet this demand, YINCAE has developed solder joint encapsulant adhesives for ball bumping applications to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. In this paper we will discuss the ball bumping process, the reliability such as strength of solder joints, drop test performance and thermal cycling performance.

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

Wafer-Level MEMS Package by Gold-Tin Bonding Method

2003 ◽  
Author(s):  
Sihai Chen ◽  
Sheng Liu ◽  
Mingxiang Chen ◽  
Tao Xiong ◽  
Daming Zhang ◽  
...  
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
Local Heating ◽  
Mems Devices ◽  
Wafer Level ◽  
Eutectic Bonding ◽  
Heating Method ◽  
To Come ◽  
Bonding Method ◽  
Global Heating

This paper reports some results for an on-going program in wafer-level MEMS package Institute of Microsystems at Huazhong University of Science and Technology. The final goal was to come up with a method usable for various types of MEMS devices in wafer level so that the low cost and high reliability can be achieved at the same time. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples are presented. The first one was first co-sputtered with Ni/Cr and then sputtered with Au metal as heating with Ni/Cr and then sputtered with Au metal as heating material, the second one was sputtered with Cr, Sn and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400°C for 20 minutes and by local heating method was applyed current of 0.8 A into the microheater. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported during the conference presentation.

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