ChipletT, A Cost-Effective, High Reliability, Embedded Die Fan-Out Package Based on Multilayer Flex Laminate with Enhanced Thermal Performance

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-32
Author(s):  
Senthil Sivaswamy ◽  
Theodore (Ted) G. Tessier ◽  
Tony Curtis ◽  
David Clark ◽  
Kazuhisa Itoi ◽  
...  
Keyword(s):  
Thermal Performance ◽  
High Reliability ◽  
Low Cost ◽  
Cost Effective ◽  
Polymer Processing ◽  
Wafer Level ◽  
Component Level ◽  
Novel Approach ◽  
Reliability Performance ◽  
Board Level

Fan-Out Wafer Level Packaging (FO-WLP) technology has been developed in recent years to overcome the limitations of Fan-in WLP (FI-WLP) packages and to add more functionality to WLP. Fan-Out packages expand the WLP market to higher pin count devices and add multiple die System in Package (SiP) capability. In this paper, a novel approach to low cost fan-out packaging based on polyimide flex circuits and wafer level Embedded Die Customization (EDC) is discussed. ChipletT refers to Fan-Out packaging. ChipsetT refers to System in Package developed with WABE (Wafer and Board Level Embedding) technology. WABE technology is based on co-lamination of multi layer polyimide flex wiring and conductive z-axis sintered metal interconnections. Using WABE technology, ultra thin fan-out packages (0.4mm) can be fabricated with lower processing costs, higher throughput and with 3D extendibility. Embedded Die Customization is performed at the wafer level and involves optimization of the die-to-embedding process by using optimized wafer level processing capabilities including polymer processing, copper plating and wafer thinning. Reliability of the ChipletT packages, both component level and board level is evaluated. ChipletT packages show high reliability in component level testing and board level testing (Thermal Cycling and Drop Testing). The thermal performance of ChipletT packages were also evaluated in this study. Thermal resistance parameters θja and θjc were simulated with and without thermal vias for both face up and face down configurations. ChipletT provides a new low cost fan out packaging option with proven component level and board level reliability performance.

Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001507-001526 ◽  
Author(s):  
Seung Wook Yoon ◽  
Yaojian Lin ◽  
Yonggang Jin ◽  
Jerome Teysseyre ◽  
Xavier Baraton ◽  
...  
Keyword(s):  
Low Cost ◽  
Standard Test ◽  
Structural Defects ◽  
Special Focus ◽  
Next Generation ◽  
Wafer Level ◽  
Process Technology ◽  
Component Level ◽  
Chip Area ◽  
Board Level

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size. This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.

Advances in Liquid Encapsulated Chip-on-Board / MCM-L Technology

1995 ◽  
Vol 390 ◽  
Author(s):  
Dale L. Robinson ◽  
David B. Clegg
Keyword(s):  
Paradigm Shift ◽  
High Reliability ◽  
Low Cost ◽  
Cost Effective ◽  
Electronics Packaging ◽  
Multichip Module ◽  
Successful Implementation ◽  
Recent Advances ◽  
History Of ◽  
Reliability Performance

ABSTRACTChip-on-Board technology (COB), or the currently more often used MCM-L acronym (MultiChip Module - Laminate), has long been touted as the low cost, high density electronics packaging choice of the future. Unfortunately, poor reliability performance in comparison to traditional plastic packaging, has been a trademark of COB/MCM-L. Recent advances in processes and materials for COB/MCM-L are providing a paradigm shift in reliability, and providing cost effective high reliability packaging solutions for COB/MCM-L. This paper examines the history of recent advances in liquid encapsulated COB/MCM-L and provides guidelines for selecting appropriate materials and processes for their successful implementation into cost effective manufacturing.

Low Cost, High Reliability WLCSP for Higher Pin Counts

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002336-002359
Author(s):  
Tony Curtis ◽  
Senthil Sivaswamy ◽  
Ronnie Yazzie ◽  
David Lawhead ◽  
Theodore G. Tessier
Keyword(s):  
Test Performance ◽  
High Reliability ◽  
Low Cost ◽  
Cycling Performance ◽  
Wafer Level ◽  
End User ◽  
The Past ◽  
Board Level ◽  
Board Level Reliability ◽  
Proper Balance

The proliferation of Wafer Level Chip Scale Packages (WLCSPs) in portable handheld products has occurred due to the minimalist form factor, high reliability and low cost packaging that they afford. As the demand for WLCSPs has grown exponentially in recent years, the industry has also been coping concurrently with the technical challenges associated with increasing array sizes and more demanding end user reliability requirements. Since handsets are inherently prone to being dropped, they are particularly susceptible to this type of component failure though striking a proper balance of mechanical robustness and thermal cycling performance has remained an ongoing industry goal. Similar to other packages, WLCSPs have transitioned over the past decade from lead-based solder alloys to Lead Free (LF) solders. LF solder connections are especially susceptible to brittle fracture and can result in variations in drop test performance from one bump structure to the next. This paper will provide an overview of process and material add-on strategies that have been shown to considerably improve mechanical robustness for bump structures or bumping applications that are inherently less robust than others. Such supplemental improvements can result in passing Board Level Reliability qualification requirements which may otherwise be elusive or have limited levels of reliability reproducibility.

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001438-001457 ◽  
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Reliability Performance ◽  
Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

scholarly journals Fabrication of Multiscale-Structure Wafer-Level Microlens Array Mold

2019 ◽  
Vol 9 (3) ◽  
pp. 487 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Xiaoxiao Wei
Keyword(s):  
Low Cost ◽  
Form Factors ◽  
Cost Effective ◽  
Microlens Array ◽  
Practical Method ◽  
Reduced Form ◽  
Wafer Level ◽  
Polycrystalline Aluminum ◽  
Microlens Arrays ◽  
Multiscale Structure

The design and manufacture of cost-effective miniaturized optics at wafer level, usingadvanced semiconductor-like techniques, enables the production of reduced form-factor cameramodules for optical devices. However, suppressing the Fresnel reflection of wafer-level microlensesis a major challenge. Moth-eye nanostructures not only satisfy the antireflection requirementof microlens arrays, but also overcome the problem of coating fracture. This novel fabricationprocess, based on a precision wafer-level microlens array mold, is designed to meet the demandfor small form factors, high resolution, and cost effectiveness. In this study, three different kinds ofaluminum material, namely 6061-T6 aluminum alloy, high-purity polycrystalline aluminum, and purenanocrystalline aluminum were used to fabricate microlens array molds with uniform nanostructures.Of these three materials, the pure nanocrystalline aluminum microlens array mold exhibited auniform nanostructure and met the optical requirements. This study lays a solid foundation for theindustrial acceptation of novel and functional multiscale-structure wafer-level microlens arrays andprovides a practical method for the low-cost manufacture of large, high-quality wafer-level molds.

High Reliability and Thermal Performance FCBGA Package

2007 ◽  
Author(s):  
Gino Hung ◽  
Ho-Yi Tsai ◽  
Chun An Huang ◽  
Steve Chiu ◽  
C. S. Hsiao
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Dielectric Material ◽  
High Reliability ◽  
Lead Free ◽  
Molding Process ◽  
Molding Compound ◽  
Reliability Performance ◽  
Low K

A high reliability and high thermal performance molding flip chip ball grid arrays structure which was improved from Terminator FCBGA®. (The structure are shown as Fig. 1) It has many advantages, like better coplanarity, high through put (multi pes for each shut of molding process), low stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand, large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free. Comparing to original Terminator FCBGA®, this structure has better thermal performance because the thermal adhesive was added between die and heat spreader instead of epoxy molding compound (EMC). The thermal adhesive has much better thermal conductivity than EMC. Furthermore, this paper also describes the process and reliability validation result.

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