Study of Different Dispensing Patterns of No-Flow Underfill Using Numerical and Experimental Methods

The conventional capillary underfill process has been a common practice in the industry, somehow the process is costly and time consuming. Thus, no-flow underfill process is developed to increase the effective lead time production since it integrates the simultaneous reflow and cure of the solder interconnect and underfill. This paper investigates the effect of different dispense patterns of no-flow underfill process by mean of numerical and experimental method. Finite volume method (FVM) was used for the three-dimensional simulation to simulate the compression flow of the no-flow underfill. Experiments were carried out to complement the simulation validity and the results from both studies have reached a good agreement. The findings show that of all three types of dispense patterns, the combined shape dispense pattern shows better chip filling capability. The dot pattern has the highest velocity and pressure distribution with values of 0.0172 m/s and 813 Pa, respectively. The high-pressure region is concentrated at the center of the chip and decreases out towards the edge. Low in pressure and velocity flow factor somehow lead to issue associated to possibility of incomplete filling or void formation. Dot dispense pattern shows less void formation since it produces high pressure underfill flow within the BGA. This paper provides reliable insight to the industry to choose the best dispense pattern of recently favorable no-flow underfill process.

Molding Recipe Study for MUF Solder Crack Improvement

In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Techniques in Extracting CSP Device from Underfilled PCB Module and Performing Solder Rework and Reballing for ATE Testing

The application of underfill materials for board level assembly has been increasing rapidly in semiconductor industry to enhance strength and reliability performance of semiconductor components in harsh environments. However, due to the intractability of the capillary underfill after curing, extracting a chip scale package (CSP) device from a printed circuit board (PCB) with a combination of mold compound and capillary underfill for ATE testing has become difficult and challenging. This poses a severe limitation to this technology regarding electrical testing and failure analysis. In order to address the challenge in extracting a CSP device from an underfilled PCB without inducing any mechanical damage, a series of sample preparation techniques has been introduced. This paper discusses the techniques in removing the fine pitch CSP device from underfilled PCB module in a relatively simple way which includes application of chemical solutions, de-soldering, residual solder remnants cleaning and reballing. The established process enables ATE testing, electrical testing and failure analysis to be performed on any CSP devices. An electrical evaluation on the efficiency of a CSP device after a series of sample preparation processes will also be highlighted.

Ball Grid Array Interconnection Properties of Solderable Polymer–Solder Composites With Low-Melting-Point Alloy Fillers

In this work, a novel ball grid array (BGA) interconnection process has been developed using solderable polymer–solder composites (SPCs) with low-melting-point alloy (LMPA) fillers to enhance the processability of the conventional capillary underfill technique and to overcome the limitations of the no-flow underfill technique. To confirm the feasibility of the proposed technique, a BGA interconnection test was performed using four types of SPCs with a different LMPA concentration (from 0 to 5 vol %). After the BGA interconnection process, the interconnection characteristics, such as morphology of conduction path and electrical properties of the BGA assemblies, were inspected and compared. The results indicated that BGA assemblies using SPC without LMPA fillers showed weak conduction path formation, including open circuit (solder bump loss) or short circuit formation because of the expansion of air voids within the interconnection area due to the relatively high reflow peak temperature. Meanwhile, assemblies using SPC with 3 vol % LMPAs showed stable metallurgical interconnection formation and electrical resistance due to the relatively low-reflow peak temperature and favorable selective wetting behavior of molten LMPAs for the solder bumps and Cu metallizations.