Temporary Wafer Bonding Materials and Processes

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001452-001476 ◽  
Author(s):  
Matthew Lueck ◽  
Alan Huffman ◽  
Marianne Butler ◽  
Dorota Temple ◽  
Phil Garrou
Keyword(s):  
Wafer Bonding ◽  
Mechanical Support ◽  
Integration Process ◽  
3D Integration ◽  
3D Ic ◽  
Ongoing Work ◽  
Different Types ◽  
Oxide Deposition ◽  
Temporary Bonding ◽  
Processing Steps

Temporary wafer bonding has been used for many years to provide mechanical support to device wafers during thinning processes. However, the advent of 2.5D and 3D integration is placing significantly higher demands on the performance of temporary bonding materials as more fabrication processes are required on progressively thinner wafers. In response, materials providers have recently developed several different types of temporary bonding solutions that seek to provide a robust carrier with a simple debond process. Typical 2.5D or 3D integration process flows will require more types of processes than just backgrinding and CMP to be done on the backside of thinned wafers. RIE, PECVD oxide deposition, lithography, and electroplating are some of the process steps that will be needed to complete the TSV interconnects. Each of these steps, and the order in which they are done, will impose certain requirements on the temporary bond material. This presentation will examine the different categories of available temporary wafer bonding solutions with regard to their bonding and debonding methods as well as their resistance to and compatibility with various BEOL processing steps. In addition, ongoing work at RTI to evaluate temporary bond materials for silicon interposer and 3D-IC applications will be presented. This work has been focusing on the interaction between these materials and the processing requirements of several photoimageable dielectrics.

The Role of Wafer Bonding in 3D Integration and Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000355-000360
Author(s):  
James Hermanowski ◽  
Greg George
Keyword(s):  
Wafer Bonding ◽  
Process Integration ◽  
3D Integration ◽  
3D Ic ◽  
Integration Schemes ◽  
Front End

There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail.

High Efficiency Single Wafer Cleaning for Wafer Bonding-Based 3D Integration Applications

2012 ◽  
Vol 187 ◽  
pp. 269-272 ◽  
Author(s):  
Don Dussault ◽  
F. Fournel ◽  
V. Dragoi
Keyword(s):  
Removal Efficiency ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Current Work ◽  
Particle Removal ◽  
3D Integration ◽  
Production Scale ◽  
Megasonic Cleaning ◽  
Wafer Cleaning ◽  
Transducer Design

Current work describes development, testing and verification of a single wafer megasonic cleaning method utilizing a transducer design that meets the extreme particle neutrality, Particle Removal Efficiency (PRE), and repeatability requirements of production scale wafer bonding and other applications requiring extremely low particle levels.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000001-000007
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Cross Sections ◽  
3D Integration ◽  
Leakage Currents ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

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