Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000698-000725 ◽  
Author(s):  
Kai Zoschke ◽  
Klaus-Dieter Lang
Keyword(s):  
Wafer Bonding ◽  
Rf Mems ◽  
Electrical Contacts ◽  
Bonding Process ◽  
Frame Structure ◽  
Back Side ◽  
Wafer Level ◽  
Free Standing ◽  
Carrier Wafer ◽  
Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001893-001912
Author(s):  
Thomas Uhrmann ◽  
Jürgen Burggraf ◽  
Harald Wiesbauer ◽  
Julian Bravin ◽  
Thorsten Matthias ◽  
...  
Keyword(s):  
Chemical Stability ◽  
High Volume ◽  
Bonding Process ◽  
Thickness Variation ◽  
Total Thickness ◽  
Process Yield ◽  
Cost Of Ownership ◽  
Temporary Bonding ◽  
Total Thickness Variation ◽  
Determining Factor

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000916-000936
Author(s):  
Jemmy Sutanto ◽  
D. H. Kang ◽  
J. H. Yoon ◽  
K. S. Oh ◽  
Michael Oh ◽  
...  
Keyword(s):  
Form Factor ◽  
System Integration ◽  
Wire Bonding ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Face To Face ◽  
Parasitic Resistance ◽  
On Chip ◽  
Packaging Cost

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

scholarly journals Silicon-Quartz Microcapillary Opto-Fluidic Platform Obtained by CMOS-Compatible Die to Wafer 200 mm Dual Bonding Process

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 1018
Author(s):  
Giuseppe Fiorentino ◽  
Ben Jones ◽  
Sophie Roth ◽  
Edith Grac ◽  
Murali Jayapala ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
System Analysis ◽  
Quartz Substrate ◽  
Microfluidic System ◽  
Bonding Process ◽  
Microfluidic Channels ◽  
Fully Integrated ◽  
Lab On Chip ◽  
Human Blood Cells ◽  
On Chip

A composite, capillary-driven microfluidic system suitable for transmitted light microscopy of cells (e.g., red and white human blood cells) is fabricated and demonstrated. The microfluidic system consists of a microchannels network fabricated in a photo-patternable adhesive polymer on a quartz substrate, which, by means of adhesive bonding, is then connected to a silicon microfluidic die (for processing of the biological sample) and quartz die (to form the imaging chamber). The entire bonding process makes use of a very low temperature budget (200 °C). In this demonstrator, the silicon die consists of microfluidic channels with transition structures to allow conveyance of fluid utilizing capillary forces from the polymer channels to the silicon channels and back to the polymer channels. Compared to existing devices, this fully integrated platform combines on the same substrate silicon microfluidic capabilities with optical system analysis, representing a portable and versatile lab-on-chip device.

Photonic network-on-chip architecture using 3D integration

2011 ◽  
Author(s):  
Aleksandr Biberman ◽  
Nicolás Sherwood-Droz ◽  
Xiaoliang Zhu ◽  
Kyle Preston ◽  
Gilbert Hendry ◽  
...  
Keyword(s):  
Network On Chip ◽  
3D Integration ◽  
Photonic Network ◽  
On Chip

High Heat Resistant Peelable Temporary Bonding Film and New Debonding System with Xe Flash Light Irradiation

2020 ◽  
Vol 2020 (1) ◽  
pp. 000302-000306
Author(s):  
Yuta Akasu ◽  
Emi Miyazawa ◽  
Tetsuya Enomoto ◽  
Yasuyuki Oyama ◽  
Shogo Sobue ◽  
...  
Keyword(s):  
Chemical Resistance ◽  
High Heat ◽  
Light Irradiation ◽  
Wafer Surface ◽  
Assembly Process ◽  
Test Vehicle ◽  
Packaging Process ◽  
Release System ◽  
Temporary Bonding ◽  
Carrier Wafer

Abstract We have developed a new temporary bonding film (TBF) and new debonding system with Xe flash light irradiation, named photonic release system, for advanced package assembly process. Since new TBF has a high Tg over 200 °C after curing and shows good chemical resistance to developer, resist stripper, and plating chemicals, no delamination, voiding, and swelling were observed after thermal and chemical treatment in the bonded structure of wafer and glass carrier. In addition, by adopting a metal-sputtered glass carrier, wafer could be debonded by Xe flash light irradiation in less than 1 ms through the glass carrier with no damage. Residual TBF on the wafer surface could be peeled off smoothly at ambient temperature without residue on the wafer. In this research, we also demonstrated the good applicability of this temporary bonding film to the typical packaging process by using test vehicle including 12 inch mold wafer and the advantage of photonic release system.

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