Packaging Issues and Solutions for Ultra-Low Power, High Efficiency GaN micro-LEDs for a Battery Free, Sub-mm2, Tetherless, Smart IoT System

2020 ◽  
Vol 2020 (1) ◽  
pp. 000181-000184
Author(s):  
F.R. Libsch ◽  
S.W. Bedell ◽  
B.C. Webb ◽  
A. Paidimarri

Abstract This paper discusses some design and implementation issues related to GaN micro-LED (μLED) incorporated into the heterogeneous packaging of IBM’s smart and secure sensor platform. For cost effective μLEDs, the sapphire substrate needs to be singulated reliably and with minimum kerf perimeter, be ultra-clean and smooth to allow back side emission without scattering, and high yielding front side flip chip bonding with 20μm C4s on 40μm pitch. The GaN μLEDs are design for low voltage/low power operation with an emission area of 20μm × 20μm with critical current density of ~10nA/μm2. Power and downlink data is delivered to the system via optical energy harvesting by on-silicon carrier photovoltaics and communication photodiode, respectively. Optical amplitude modulated uplink communication by heterogeneous packaging of the GaN μLED with a 14nm CMOS smart chip will be detailed and demonstrated in presentation.

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 928 ◽  
Author(s):  
Taehoon Kim ◽  
Sivasundar Manisankar ◽  
Yeonbae Chung

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.


2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.


2006 ◽  
Vol 129 (3) ◽  
pp. 298-303 ◽  
Author(s):  
V. M. Andreev ◽  
A. S. Vlasov ◽  
V. P. Khvostikov ◽  
O. A. Khvostikova ◽  
P. Y. Gazaryan ◽  
...  

Results of a solar thermophotovoltaic (STPV) system study are reported. Modeling of the STPV module performance and the analysis of various parameters influencing the system are presented. The ways for the STPV system efficiency to increase and their magnitude are considered such as: improvement of the emitter radiation selectivity and application of selective filters for better matching the emitter radiation spectrum and cell photoresponse; application of the cells with a back side reflector for recycling the sub-band gap photons; and development of low-band gap tandem TPV cells for better utilization of the radiation spectrum. Sunlight concentrator and STPV modules were designed, fabricated, and tested under indoor and outdoor conditions. A cost-effective sunlight concentrator with Fresnel lens was developed as a primary concentrator and a secondary quartz meniscus lens ensured the high concentration ratio of ∼4000×, which is necessary for achieving the high efficiency of the concentrator–emitter system owing to trap escaping radiation. Several types of STPV modules have been developed and tested under concentrated sunlight. Photocurrent density of 4.5A∕cm2 was registered in a photoreceiver based on 1×1cm2GaSb cells under a solar powered tungsten emitter.


2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.


Author(s):  
Carmine Paolino ◽  
Fabio Pareschi ◽  
Mauro Mangia ◽  
Riccardo Rovatti ◽  
Gianluca Setti

2020 ◽  
Vol 39 (12) ◽  
pp. 6034-6057
Author(s):  
Vitawat Sittakul ◽  
S. Vijayalakshmi ◽  
V. Nagarajan ◽  
K. Sakthidasan Sankaran ◽  
Sakthivel Sankaran

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