Quality and Reliability of 3D High-Performance Heterogeneous Integration through Die Stacking
This paper studies package reliability for the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration) delivering up to 2.78 Tb/s transceiver bandwidth. Each device is packaged on a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. 3D thermal-mechanical simulations are built to analyze package warpage, low-k stresses, microbumps and C4 bumps fatigue as well as BGA ball reliability. Different substrate sizes and designs, lid designs, lid materials and C4 bump underfill materials are investigated in order to optimize package reliability. LTCC ceramic package reduces fatigue in C4 bumps when increasing the risk for BGA balls to fail in thermal stressing. Hence, lid design and C4 bump underfill material are optimized to increase fatigue life for BGA balls. Simulation results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.