Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages

2016 ◽  
Vol 2016 (S2) ◽  
pp. S1-S22
Author(s):  
Dongkai Shangguan ◽  
Yao Jian Lin ◽  
Won Kyung Choi ◽  
Seng Guan Chow ◽  
Seung Wook Yoon
Keyword(s):  
Experimental Study ◽  
Form Factor ◽  
Structural Design ◽  
Heat Dissipation ◽  
Functional Integration ◽  
Thermal Characterization ◽  
Structural Defects ◽  
Wafer Level ◽  
Factors Affecting ◽  
Ball Grid Array Packages

To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also facilitates integration of multiple dies vertically and horizontally in a single package without using substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in eWLB fan-out WLP with multilayer RDL's. Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Warpage, die cracking and other failures were characterized through metrology measurements and electrical tests. Board assembly processes (including SMT, underfill, etc.) were also studied. The influence of materials and structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001438-001457 ◽  
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Reliability Performance ◽  
Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

Packaging and Integration Strategy for mm-Wave Products

2018 ◽  
Vol 2018 (1) ◽  
pp. 000252-000258 ◽  
Author(s):  
Urmi Ray ◽  
NJ Cho ◽  
YC Kim ◽  
SW Yoon ◽  
WK Choi ◽  
...  
Keyword(s):  
Form Factor ◽  
Antenna Arrays ◽  
System Integration ◽  
High Performance ◽  
Heat Dissipation ◽  
System Level ◽  
Wafer Level ◽  
Automotive Radar ◽  
Rf Transceiver ◽  
Trade Offs

Abstract This paper is a follow on to the paper presented at the IMAPS 14th International Conference DEVICE PACKAGING and will provide more comprehensive case studies of few different system integration strategies for high frequency packaging. The packaging options vary widely based on the end market requirements, from performance, thermal, types and numbers of antenna arrays as well as the RF transceiver ICs. Tied closely to these performance related requirements is competing trade-offs of reliability, form factor and cost. We present assessment of packaging structures for (a) high performance mm-Wave network product and (b) consumer/mobile product and (c) automotive radar product. The former (a) is generally not challenged by form factor and can be enhanced by the addition of more antenna arrays and RFICs. However, care has to be taken to address the thermal solutions for effective heat dissipation as well as manufacturability issues as the package size may target ~400mm2 for Gen 1 and double or triple the area for subsequent generations. For (b), the primary drivers are cost and form factor. To manage antenna propagation and losses in a constrained form factor, mobile products generally require antenna in package (AiP) integration. The integration of the antenna within the same package as the RF IC greatly reduces the difficulty at the system level. This approach coupled to aggressive miniaturization of the antenna itself, using the same substrate technologies as the SiP leads to a new class of sub-systems termed Antenna in Package (AiP). This is extremely challenging from design, manufacturability and test perspectives. For example, Fan out wafer level packaging, such as eWLB packaging provides extremely smooth copper surfaces with tight etch tolerance compared to standard laminate based packaging. However, having multiport antenna structures fabricated in fan out technology with inductance matching and efficient ground ports, continue to be problematic. Hence adoption of 3D structures, in conjunction with SIP integration (with inductors and IPDs) can potentially provide relief. Inductors can also be built into the eWLB structure using the RDL as well as in the laminate packages using substrate embedded thin film cores.

Design and experimental study on a new heat dissipation method for watch-phones

2021 ◽  
Author(s):  
Wenjie Zhou ◽  
Yong Li ◽  
Zhaoshu Chen ◽  
Yuying Yan ◽  
Hanyin Chen
Keyword(s):  
Experimental Study ◽  
Heat Dissipation

Mechanisms overview of Thermocompression Process for Copper Metal Bonding

2013 ◽  
Vol 1559 ◽  
Author(s):  
Paul Gondcharton ◽  
Floriane Baudin ◽  
Lamine Benaissa ◽  
Bruno Imbert
Keyword(s):  
Functional Integration ◽  
Pure Copper ◽  
Surface Preparation ◽  
Native Oxide ◽  
Process Window ◽  
Wafer Level ◽  
Metallic Oxide ◽  
Copper Diffusion ◽  
Thermomechanical Stress ◽  
Metal Bonding

ABSTRACTWafer level metal bonding involving copper material is widely used to achieve 3D functional integration of ICs and ensure effective packaging sealing for various applications. In this paper we focus on thermocompression bonding technology where temperature and pressure are used in parallel to assist the bonding process. More specifically a broad range of conditions was explored and interesting results were observed and are reported. Indeed, despite a relatively high roughness, the presence of a native oxide and the lack of surface preparation, there still exists a process window where wafer level bonding is allowed. In these conditions, limiting the bonding mechanisms to basic copper diffusion is no longer satisfactory. In this study, a specific scenario inspired by both wafer bonding and metal welding state of the art is put forward. Accordingly, pure copper diffusion through the bonding interface is lined with plastic deformation and metallic oxide fracture. In addition, polycrystalline film deformation due to thermomechanical stress is highlighted and grain growth and voiding formation are observed and confirmed.

Experimental Study on Heat Pipe Radiator in Cooling Electronic Apparatus

2012 ◽  
Vol 197 ◽  
pp. 216-220
Author(s):  
Zhong Chao Zhao ◽  
Rui Ye ◽  
Gen Ming Zhou
Keyword(s):  
Heat Transfer ◽  
Experimental Study ◽  
Heat Pipe ◽  
Heat Dissipation ◽  
Heat Transfer Performance ◽  
Electronic Device ◽  
Transfer Performance ◽  
Air Velocity ◽  
Electronic Apparatus ◽  
Operational Temperature

To solve the cooling problem in modern electronic device, a kind of heat pipe radiator was designed and manufactured in this paper. The heat transfer performance of heat pipe radiator and its relationship with air velocity were investigated by experimental method. The experimental results show that the heat pipe radiator can meet the temperature requirement of electronic device with the power range from 40W to 160W. To keep the operational temperature of electronic device with power of 160W under 75°C，the air velocity should be keep at 1.7m/s. The heat dissipation performance of heat pipe radiator was enhanced with the air velocity increased from 0.2m/s to 1.7m/s.for the electronic equipment with power of 160W.

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