Packaging and Integration Strategy for mm-Wave Products

2018 ◽  
Vol 2018 (1) ◽  
pp. 000252-000258 ◽  
Author(s):  
Urmi Ray ◽  
NJ Cho ◽  
YC Kim ◽  
SW Yoon ◽  
WK Choi ◽  
...  
Keyword(s):  
Form Factor ◽  
Antenna Arrays ◽  
System Integration ◽  
High Performance ◽  
Heat Dissipation ◽  
System Level ◽  
Wafer Level ◽  
Automotive Radar ◽  
Rf Transceiver ◽  
Trade Offs

Abstract This paper is a follow on to the paper presented at the IMAPS 14th International Conference DEVICE PACKAGING and will provide more comprehensive case studies of few different system integration strategies for high frequency packaging. The packaging options vary widely based on the end market requirements, from performance, thermal, types and numbers of antenna arrays as well as the RF transceiver ICs. Tied closely to these performance related requirements is competing trade-offs of reliability, form factor and cost. We present assessment of packaging structures for (a) high performance mm-Wave network product and (b) consumer/mobile product and (c) automotive radar product. The former (a) is generally not challenged by form factor and can be enhanced by the addition of more antenna arrays and RFICs. However, care has to be taken to address the thermal solutions for effective heat dissipation as well as manufacturability issues as the package size may target ~400mm2 for Gen 1 and double or triple the area for subsequent generations. For (b), the primary drivers are cost and form factor. To manage antenna propagation and losses in a constrained form factor, mobile products generally require antenna in package (AiP) integration. The integration of the antenna within the same package as the RF IC greatly reduces the difficulty at the system level. This approach coupled to aggressive miniaturization of the antenna itself, using the same substrate technologies as the SiP leads to a new class of sub-systems termed Antenna in Package (AiP). This is extremely challenging from design, manufacturability and test perspectives. For example, Fan out wafer level packaging, such as eWLB packaging provides extremely smooth copper surfaces with tight etch tolerance compared to standard laminate based packaging. However, having multiport antenna structures fabricated in fan out technology with inductance matching and efficient ground ports, continue to be problematic. Hence adoption of 3D structures, in conjunction with SIP integration (with inductors and IPDs) can potentially provide relief. Inductors can also be built into the eWLB structure using the RDL as well as in the laminate packages using substrate embedded thin film cores.

Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

CoC (Chip on Chip) or FtoF (Face to Face) - PossumTM Technology for 3D MEMS and ASIC eliminating the need of TSV or Wire Bonding

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000916-000936
Author(s):  
Jemmy Sutanto ◽  
D. H. Kang ◽  
J. H. Yoon ◽  
K. S. Oh ◽  
Michael Oh ◽  
...  
Keyword(s):  
Form Factor ◽  
System Integration ◽  
Wire Bonding ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Face To Face ◽  
Parasitic Resistance ◽  
On Chip ◽  
Packaging Cost

This paper describes the ongoing 3 years research and development at Amkor Technology on CoC (Chip on Chip)/FtF (Face to Face) – PossumTM technology. This technology has showed a lot of interests from the microelectronics customers/industries because of its various advantages, which include a) providing smaller form factor (SFF) to the final package, b) more functionalities (dies) can be incorporated/assembled in one package, c) improving the electrical performance - including lower parasitic resistance, lower power, and higher frequency bandwidth, and d) Opportunity for lower cost 3D system integration. Unlike other 3D Packaging technology (e.g. using TSV (Through Silicon Vias)) that requires some works in the front stream (wafer foundry) level, needs new capitals for machines/equipments, and needs modified assembly lines; CoC/FtF technology uses the existing flip Chip Attach (C/A) or TC (Thermal Compression) equipment/machine to perform the assembly joint between the two dies, which are named as the mother (larger) die and the daughter (smaller) die. Furthermore, the cost to assemble CoC/FtF is relatively inexpensive while the applications are very wide and endless, which include the 3D integration of MEMS and ASIC. The current MEMS packaging and test cost contributes about 35 to 45% to the overall MEMS unit cost. WLC (Wafer Level Capping) with wire bonding have been widely used for mass production for accelerometer (e.g. ADI and Motorola), gyroscope (e.g. Bosch and Invensense), and oscillator /timer (e.g. Discera). The WLC produce drawbacks of a large form factor and the increase in the capacitive and electrical resistances. Currently, the industries have been developing a new approach of 3D WLP (Wafer Level Packaging) by using a) TSV MEMS cap with wire bonding (e.g. Discera), b) TSV MAME cap with solder bump (e.g. Samsung, IMEC, and VTI), and c) TSV MEMS wafer/die with cap (e.g. Silex Microsystems). The needs of TSVs in the 3D WLP will add the packaging cost and reduce the design flexibility is pre-TSV wafer is used. “Amkor CoC/FtoF – PossumTM” is an alternative technology for 3D integration of MEMS and ASIC. CoC/FtoF – PossumTM does not require TSV or wire bonding; Miniaturizing form factor of 1.5 mm x 1.5 mm x 0.95 mm (including the package) of MEMS and ASIC can be achieved by using CoC/FtoF – PossumTM while Discera's design of 3D WLP requires substrate size > 2 mm x 2 mm. CoC/FtoF – PossumTM will likely produce packaging cost which is lower than WLC or 3D WLP – TSV at the same time the customer is benefited from smaller FF and reduced electrical/parasitic resistance. CoC/FtoF – PossumTM can be applied to any substrates including FCBGA and laminate. This technology also can be applied to package multiple MEMS microsensors, together with ASIC, microcontroller, and wireless RF to realize the 3D system integration.

Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages

2016 ◽  
Vol 2016 (S2) ◽  
pp. S1-S22
Author(s):  
Dongkai Shangguan ◽  
Yao Jian Lin ◽  
Won Kyung Choi ◽  
Seng Guan Chow ◽  
Seung Wook Yoon
Keyword(s):  
Experimental Study ◽  
Form Factor ◽  
Structural Design ◽  
Heat Dissipation ◽  
Functional Integration ◽  
Thermal Characterization ◽  
Structural Defects ◽  
Wafer Level ◽  
Factors Affecting ◽  
Ball Grid Array Packages

To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also facilitates integration of multiple dies vertically and horizontally in a single package without using substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in eWLB fan-out WLP with multilayer RDL's. Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Warpage, die cracking and other failures were characterized through metrology measurements and electrical tests. Board assembly processes (including SMT, underfill, etc.) were also studied. The influence of materials and structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.

Low-cost eWLB packaging for automotive radar MMICs in the 76–81 GHz range

2013 ◽  
Vol 5 (1) ◽  
pp. 25-34 ◽  
Author(s):  
J. Böck ◽  
M. Wojnowski ◽  
C. Wagner ◽  
H. Knapp ◽  
W. Hartner ◽  
...  
Keyword(s):  
System Integration ◽  
Low Cost ◽  
Wafer Level ◽  
Automotive Radar ◽  
Package Design ◽  
Radar Sensors ◽  
Radar Systems ◽  
Plastic Package ◽  
Rf Performance ◽  
Near Future

Embedded wafer-level ball grid array (eWLB) is investigated as a low-cost plastic package for automotive radar applications in the 76–81 GHz range. Low transmission losses from chip to package and board are achieved by appropriate circuit and package design. Special measures are taken to effectively remove the heat from the package and to optimize the package process to achieve automotive quality targets. A 77 GHz radar chip set in eWLB package is developed, which can be applied on the system board using standard solder reflow assembly. These radar MMICs provide excellent radio frequency (RF) performance for the next generation automotive radar sensors. The potential for even higher system integration is shown by a radar transceiver with antennas integrated in the eWLB package. These results demonstrate that eWLB technology is an attractive candidate to realize low-cost radar systems and to enable radar safety affordable for everyone in the near future.

A SiGe-based fully-integrated 122-GHz FMCW radar sensor in an eWLB package

2017 ◽  
Vol 9 (6) ◽  
pp. 1219-1230 ◽  
Author(s):  
Muhammad Furqan ◽  
Faisal Ahmed ◽  
Reinhard Feger ◽  
Klaus Aufinger ◽  
Walter Hartner ◽  
...  
Keyword(s):  
Antenna Arrays ◽  
High Performance ◽  
Continuous Wave ◽  
Supply Voltage ◽  
Angular Position ◽  
Frequency Multiplier ◽  
Wafer Level ◽  
Range Resolution ◽  
Fmcw Radar ◽  
Bicmos Technology

High-performance SiGe HBTs and advancements in packaging processes have enabled system-in-package (SiP) designs for millimeter-wave applications. This paper presents a 122-GHz bistatic frequency modulated continuous wave (FMCW) radar SiP. The intended applications for the SiP are short-range distance and angular position measurements as well as communication links between cooperative radar stations. The chip is realized in a 130-nm SiGe BiCMOS technology and is based on a fully differential frequency-multiplier chain with in phase quadrature phase receiver and a binary phase shift keying modulator in the transmit chain. On-wafer measurement results show a maximum transmit output power of 2.7 dBm and a receiver gain of 11 dB. The chip consumes a DC power of 570 mW at a supply voltage of 3.3 V. The fabricated chip is integrated in an embedded wafer level ball grid array (eWLB) package. Transmit/receive rhombic antenna arrays with eight elements are designed in two eWLB packages with and without backside metal, with a measured peak gain of 11 dBi. The transceiver chip size is 1.8 mm × 2 mm, while the package size is 12 mm × 6 mm, respectively. FMCW measurements have been conducted with a sweep bandwidth of up to 17 GHz and a measured range resolution of 1.5 cm has been demonstrated. 2D positions of multiple targets have been computed using two coherently linked radar stations.

3D Process Integration – Requirements and Challenges

2008 ◽  
Vol 1112 ◽  
Author(s):  
Juergen Max Wolf ◽  
Armin Klumpp ◽  
Kai Zoschke ◽  
Robert Wieland ◽  
Lars Nebrich ◽  
...  
Keyword(s):  
System Integration ◽  
New Technologies ◽  
Process Integration ◽  
High Volume ◽  
System Level ◽  
Wafer Level ◽  
System Architectures ◽  
Future System ◽  
3D Packaging ◽  
Third Dimension

AbstractHeterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Power Efficiency ◽  
High Performance ◽  
Electrical Characterization ◽  
Cost Effective ◽  
Electrical Performance ◽  
Wearable Electronics ◽  
Wafer Level ◽  
Low Profile ◽  
Line Spacing

FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

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