Direct write lithography approach for Panel Level Package

2016 ◽  
Vol 2016 (1) ◽  
pp. 000406-000409 ◽  
Author(s):  
Hiroshi Matsui ◽  
Tatsuya Nagao ◽  
Yoshinao Norimitsu
Keyword(s):  
Production Cost ◽  
Great Difficulty ◽  
Direct Write ◽  
Wafer Level ◽  
Reduce Production Cost ◽  
Lithography Process ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Substrate Size

Abstract Fan-out processing a is booming technology at wafer level packaging. However, chip last process in fan-out gives great difficulty to lithography. At the same time, the industry is looking for increasing substrate size in order to reduce production cost. Direct write technology shall be the key lithography process having both flexibility and compatibility for large size substrate.

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001438-001457 ◽  
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Dielectric Materials ◽  
Structural Defects ◽  
Temperature Cycle ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Large Size ◽  
Reliability Performance ◽  
Robust Reliability

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

scholarly journals Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Che-Jung Chang ◽  
Der-Chiang Li ◽  
Wen-Li Dai ◽  
Chien-Chih Chen
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing System ◽  
Grey System Theory ◽  
Grey Model ◽  
Grey System ◽  
Wafer Level ◽  
Short Term ◽  
Packaging Process ◽  
Wafer Level Packaging

The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1) grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.

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