Reduction of Thermal Stress - Part III: UBM and Passivation Thickness Optimization

2017 ◽  
Vol 2017 (1) ◽  
pp. 000694-000698
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Finite Element Analysis ◽  
Solder Ball ◽  
Coefficient Of Thermal Expansion ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Element Analysis ◽  
Wafer Level Packaging ◽  
Two Factors ◽  
Process Factors ◽  
Significant Factors

Abstract Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps. Finite Element Analysis (FEA) of such designs can help identify possible root causes early in the design process and i.e. before actual fabrication. This would help save valuable prototyping & testing costs. In Part III of this series of FEA studies, two factors i.e. silicon nitride thickness (from the BEOL process), and the Under Bump Metalization (UBM) thickness (from the WLP process) were identified as significant factors in changing the maximum first principal stress levels in the passivation layer.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties

2021 ◽  
Vol 21 (5) ◽  
pp. 2987-2991
Author(s):  
Geumtaek Kim ◽  
Daeil Kwon
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Material Properties ◽  
Coefficient Of Thermal Expansion ◽  
Input Output ◽  
Wafer Level ◽  
High Input ◽  
Element Analysis ◽  
Packaging Process ◽  
Wafer Level Packaging

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Verification of Faulty Mechanism for Fan-Out Wafer Level Package Using Numerical Analysis

2015 ◽  
Vol 789-790 ◽  
pp. 609-612
Author(s):  
Hyung Seok Yoon ◽  
Insu Jeon
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Performance Improvement ◽  
Solder Ball ◽  
Wafer Level ◽  
Element Analysis ◽  
Semiconductor Chip ◽  
The Finite Element Analysis ◽  
Deformational Behavior ◽  
Wafer Level Package

The manufactures of the ultra-thin and smaller semiconductor chip are required over the portable electric devices. The investigation of Fan-out wafer level package (FOWLP) is used widely, among the performance improvement and miniaturization technologies. In this paper, we obtained lots of crack near the passivation (PSV) and redistributed layer (RDL) region of FOWLP during the reliability evaluation of thermal cycling test (TCT). The generated stress and deformational behavior was observed through 2D finite-element analysis. The concentrated stress and deformational behavior are observed around the Solder ball edge and RDL & PSV edges. The crack was observed experimentally as well. The verification of the mechanism for crack generation and the validity of the finite-element analysis were verified by the structural analysis.

scholarly journals Investigation on Die Crack in a Stacked Die Package Using Finite Element Analysis

2021 ◽  
pp. 83-91
Author(s):  
Jefferson Talledo
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Coefficient Of Thermal Expansion ◽  
Crack Problem ◽  
Element Analysis ◽  
Robust Solution ◽  
Die Attach ◽  
Die Stress ◽  
Cte Mismatch ◽  
Semiconductor Packages

Die crack is one of the problems in stacked die semiconductor packages. As silicon dies become thinner in such packages due to miniaturization requirement, the tendency to have die crack increases. This study presents the investigation done on a die crack issue in a stacked die package using finite element analysis (FEA). The die stress induced during the package assembly processes from die attach to package strip reflow was analyzed and compared with the actual die crack failure in terms of the location of maximum die stress at unit level as well as strip level. Stresses in the die due to coefficient of thermal expansion (CTE) mismatch of the package component materials and mechanical bending of the package in strip format were taken into consideration. Comparison of the die stress with actual die crack pointed to strip bending as the cause of the problem and not CTE mismatch. It was found that the die crack was not due to the thermal processes involved during package assembly. This study showed that analyzing die stress using FEA could help identify the root cause of a die crack problem during the stacked die package assembly and manufacturing as crack occurs at locations of maximum stress. The die crack mechanism can also be understood through FEA simulation and such understanding is very important in coming up with robust solution.

Development of G-Helix Structure as Off-Chip Interconnect

2004 ◽  
Vol 126 (2) ◽  
pp. 237-246 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
Mechanical Performance ◽  
Coefficient Of Thermal Expansion ◽  
Mechanical Analysis ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Package Weight ◽  
Mechanical Compliance ◽  
Cte Mismatch

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

Finite Element Analysis of Thermal Stress for Femoral Prosthesis

2013 ◽  
Vol 750-752 ◽  
pp. 2212-2215
Author(s):  
Mo Nan Wang
Keyword(s):  
Finite Element Method ◽  
Finite Element Analysis ◽  
Finite Element ◽  
Coefficient Of Thermal Expansion ◽  
Physical Property ◽  
Prosthetic Material ◽  
Femoral Prosthesis ◽  
Interface Failure ◽  
Element Analysis ◽  
Selection Of

Based on the thermo elasticity theory, the stress of femur prosthesis system was analyzed using finite element method. An evaluation for the selection of prosthetic material was presented after discussing the thermo physical property of material which had an effect on the stress of femur prosthesis system. The results indicate that the interface failure is the primary failure form of the femoral prosthesis system and the interface failure is accelerated for the reason of the thermal effect. So the prosthesis with low coefficient of thermal expansion should be selected which can moderate the interface failure in the certain degree.

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