C<sub>60</sub>-Nanowire Two-State Resistance Switching

Background: Switches are important component in electrical system. The switches needs to have the advantages of low ON-state resistance, very high OFF-state resistance, high isolation, no leakage current, less power loss, fast switching, high linearity, small size, arcless and low cost in bulk production. Also these switches have to be reliable and environmental friendly. Methods: In this paper, macro and microswitches for power applications are extensively reviewed and summarized. Various types of switches such as mechanical, solid-state, hybrid and micromechanical switches have been used for power applications are reviewed. The importance and challenge in achieving arcless switching is presented. Results: The use of micromechanical switches for power applications, actuation techniques, switching modes, reliability and lifetime are also reviewed. The modeling and design challenges are also reviewed. Conclusion: The applications of micromechanical switches shows that the switches can reduce the leakage current in battery operated systems and reduce the size of the system considerably.

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Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽

10.3390/electronics10060735 ◽

2021 ◽

Vol 10 (6) ◽

pp. 735

Author(s):

Fortunato Pezzimenti ◽

Hichem Bencherif ◽

Giuseppe De Martino ◽

Lakhdar Dehimi ◽

Riccardo Carotenuto ◽

...

Keyword(s):

Drain Current ◽

Oxide Semiconductor ◽

Temperature Dependent ◽

Channel Mobility ◽

Blocking Voltage ◽

Current Voltage ◽

Wide Range ◽

Temperature Ranges ◽

Joint Contribution ◽

State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

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Effects of bracket design on critical contact angle

The Angle Orthodontist ◽

10.2319/080112-621.1 ◽

2013 ◽

Vol 83 (5) ◽

pp. 877-884 ◽

Cited By ~ 4

Author(s):

Xiaomo Liu ◽

Peng Ding ◽

Jiuxiang Lin

Keyword(s):

Contact Angle ◽

Stainless Steel ◽

Linear Regression ◽

Resistance To Sliding ◽

The Relationship ◽

State Resistance ◽

Critical Contact ◽

Bracket Design

ABSTRACT Objective: To explore how the position of the bracket slots relative to the archwire influences the friction between them, and how bracket design affects the critical contact angle (θc). Materials and Methods: Two kinds of stainless steel archwires (0.016 and 0.019 × 0.025-inch) were tested against four kinds of brackets (Transmission Straight Archwire bracket, Domestic MBT bracket, Tip-Edge Plus bracket, and BioQuick self-ligation bracket) in the dry state. Resistance to sliding (RS) was measured as an increase in contact angle (θ). The value of θc was calculated by two linear regression lines. Results: Friction remained stable when θ < θc, then increased linearly when θ > θc. The θc values of the Tip-Edge Plus bracket and Transmission Straight Archwire bracket were significantly larger than those for the Domestic MBT bracket and BioQuick self-ligation bracket. Conclusions: The relationship between the archwire and bracket slot significantly affects the resistance to sliding. The “edge-off” structure of the Tip-Edge Plus bracket and Transmission Straight Archwire bracket could help to increase the θc value, and to expand the passive configuration range.

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Mechanism Analysis of Dynamic On-State Resistance Degradation for a Commercial GaN HEMT Using Double Pulse Test

Electronics ◽

10.3390/electronics10101202 ◽

2021 ◽

Vol 10 (10) ◽

pp. 1202

Author(s):

Wei Wang ◽

Yan Liang ◽

Minghui Zhang ◽

Fang Lin ◽

Feng Wen ◽

...

Keyword(s):

Gradual Increase ◽

Dynamic Resistance ◽

Mechanism Analysis ◽

Pulse Test ◽

Gan Hemt ◽

Resistance Degradation ◽

Dielectric Model ◽

Leaky Dielectric Model ◽

State Resistance ◽

Stress Voltage

The dynamic on-resistance (RON) behavior of one commercial GaN HEMT device with p-GaN gate is investigated under hard-switching conditions. The non-monotonic performance of dynamic RON with off-state voltage ranging from 50 to 400 V is ascribed to the “leaky dielectric” model. The highest normalized RON value of 1.22 appears at 150 and 200 V. The gradual increase and following maximum of dynamic RON are found when the device is exposed to a stress voltage for an extended stress time under 100 and 200 V, which is due to a much longer trapping time compared to detrapping time related to deep acceptors and donors. No obvious RON degradation, thanks to the suppressed trapping effect, is observed at higher VDS. From the multi-pulse test, the dynamic RON is seen to be insensitive to the frequency. It is demonstrated that the leakage, especially under source and drain contact, is a key issue in the dynamic resistance degradation.

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Ratio-based multi-level resistive memory cells

Scientific Reports ◽

10.1038/s41598-020-80121-7 ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

Miguel Angel Lastras-Montaño ◽

Osvaldo Del Pozo-Zamudio ◽

Lev Glebsky ◽

Meiran Zhao ◽

Huaqiang Wu ◽

...

Keyword(s):

Error Probability ◽

Resistance Switching ◽

Closed Form Expression ◽

Memory Cells ◽

Resistive Memory ◽

Worst Case ◽

Information Encoding ◽

Bit Error Probability ◽

Multi Level ◽

Switching Devices

AbstractRatio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to $$x^2$$ x 2 at the best case and $$x^{\sqrt{2}}$$ x 2 at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10$$\times$$ × , while achieving the same bit error probability.

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