Trap-assisted tunneling on extended defects in tunnel field-effect transistors

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EC03 ◽  
Author(s):  
Manfred Reiche ◽  
Martin Kittler ◽  
Hartmut Übensee ◽  
Michael Krause ◽  
Eckhard Pippel
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Extended Defects ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling

scholarly journals Compact Trap-Assisted-Tunneling Model for Line Tunneling Field-Effect-Transistor Devices

2020 ◽  
Vol 10 (13) ◽  
pp. 4475
Author(s):  
Faraz Najam ◽  
Yun Seop Yu
Keyword(s):  
Experimental Data ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Potential Profile ◽  
Relaxation Energy ◽  
Tunneling Model ◽  
Compact Formulation ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling

Trap-assisted-tunneling (TAT) is a well-documented source of severe subthreshold degradation in tunneling field-effect-transistors (TFET). However, the literature lacks in numerical or compact TAT models applied to TFET devices. This work presents a compact formulation of the Schenk TAT model that is used to fit experimental drain-source current (Ids) versus gate-source voltage (Vgs) data of an L-shaped and line tunneling type TFET. The Schenk model incorporates material-dependent fundamental physical constants that play an important role in influencing the TAT generation (GTAT) including the lattice relaxation energy, Huang–Rhys factor, and the electro-optical frequency. This makes fitting any experimental data using the Schenk model physically relevant. The compact formulation of the Schenk TAT model involved solving the potential profile in the TFET and using that potential profile to calculate GTAT using the standard Schenk model. The GTAT was then approximated by the Gaussian distribution function for compact implementation. The model was compared against technology computer-aided design (TCAD) results and was found in reasonable agreement. The model was also used to fit an experimental device’s Ids–Vgs characteristics. The results, while not exactly fitting the experimental data, follow the general experimental Ids–Vgs trend reasonably well; the subthreshold slope was loosely similar to the experimental device. Additionally, the ON-current, especially to make a high drain-source bias model accurate, can be further improved by including effects such as electrostatic degradation and series resistance.

Atomistic modeling trap-assisted tunneling in hole tunnel field effect transistors

2018 ◽  
Vol 123 (17) ◽  
pp. 174504 ◽  
Author(s):  
Pengyu Long ◽  
Jun Z. Huang ◽  
Michael Povolotskyi ◽  
Prasad Sarangapani ◽  
Gustavo A. Valencia-Zapata ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Atomistic Modeling ◽  
Trap Assisted Tunneling ◽  
Assisted Tunneling

scholarly journals Nanowire Tunnel Field Effect Transistors at High Temperature

2013 ◽  
Vol 8 (2) ◽  
pp. 110-115
Author(s):  
Márcio D. V. Martino ◽  
Felipe S. Neves ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
Rita Rooyackers ◽  
...  
Keyword(s):  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Transport Mechanisms ◽  
Temperature Influence ◽  
Subthreshold Slope ◽  
Band To Band Tunneling ◽  
Trap Assisted Tunneling ◽  
Working Principle

The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working principle and this analysis was compared to experimental data obtained for temperature ranging from 300 to 420 K. This methodology was performed for different nanowire diameters and bias conditions, leading to a deep investigation of parameters such as the ratio of on-state and off-state current (ION/IOFF) and the subthreshold slope (S). Three different transport mechanisms (band-to-band tunneling, Shockley-Read-Hall generation/recombination and trap-assisted tunneling) were highlighted to explain the temperature influence on the drain current. As the final step, subthreshold slope values for each configuration were compared to the room temperature. Therefore, it was observed that larger nanowire diameters and lower temperatures tended to increase ION/IOFF ratio. Meanwhile, it was clear that band-to-band tunneling prevailed for higher gate voltage bias, resulting in a much slighter temperature effect on the drain current.

Influence of Structural and Electrical Characteristics of Extended Defects on GaAs Field Effect Transistors

1987 ◽  
Vol 104 ◽  
Author(s):  
M. Van Hove ◽  
W. De Raedt ◽  
M. De Potter ◽  
M. Van Rossum ◽  
J. L. Weyher
Keyword(s):  
Systematic Study ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Extended Defects ◽  
Electrical Characteristics ◽  
Systematic Mapping ◽  
Gaas Substrates ◽  
Lec Gaas ◽  
Induced Defects ◽  
Processing Steps

ABSTRACTThe paper presents a systematic study of grown-in and process-induced defects on LEC GaAs substrates. Defects have been revealed by photoetching the wafers with diluted Sirti-like solutions after various processing steps. MESFET arrays have been processed on the wafers and a systematic mapping of the I-V characteristics has been performed. A correlation between various defect configurations and the FET threshold voltage shifts has been established.

Microstructural Characterization of SiGe Heterolayers

1991 ◽  
Vol 239 ◽  
Author(s):  
N. David Theodore ◽  
Peter Fejes ◽  
Mamoru Tomozane ◽  
Ming Liaw
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Infrared Detectors ◽  
Field Effect ◽  
Strain Energy ◽  
Field Effect Transistors ◽  
Microstructural Characterization ◽  
Bipolar Transistors ◽  
Misfit Dislocations ◽  
Extended Defects

ABSTRACTSiGe is of interest for use in heterojunction-bipolar transistors, infrared detectors and field-effect transistors. In this study, graded SiGe heterolayers grown on Si, and heterolayers grown on SIMOX by CVD, were characterized using TEM. The graded-heterolayers consisted of ten layers of Si1-xGex on substrate silicon. Misfit dislocations were present at interfaces in the bottom 4–5 layers of the heterostructure. This conforms with predictions from qualitative strain-energy considerations. The greatest density of misfit dislocations was present at the Si1-xGex interface between the bottom two layers of the heterostructure. Dislocations were observed to extend out of the interface and up into the heterolayer structure. The defects were found to interact with interfaces in the structure and finally cease extending upwards towards the surface of the wafer. In addition to graded heterolayers, SiGe heterolayers grown on SIMOX were also investigated. The structures consisted of epi-silicon grown on a Si/Si1-xGex superlattice which was in turn grown on a Si/SiO2 (SIMOX) structure. The behavior of defects in the layers was of interest. TEM characterization showed a large density of extended-defects present in the layers. Dislocations were observed to originate at the SIMOX oxide/Si interface, propagate up through the SiGe superlattice and into the epi-Si layer. Some dislocations were found to interact with the SiGe superlattice and cease propagating up towards the top of the wafer. SiGe superlattices with a higher concentration of Ge are more effective in reducing defect propagation towards the surface of the wafer.

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