scholarly journals Nanowire Tunnel Field Effect Transistors at High Temperature

2013 ◽  
Vol 8 (2) ◽  
pp. 110-115
Author(s):  
Márcio D. V. Martino ◽  
Felipe S. Neves ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
Rita Rooyackers ◽  
...  
Keyword(s):  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Transport Mechanisms ◽  
Temperature Influence ◽  
Subthreshold Slope ◽  
Band To Band Tunneling ◽  
Trap Assisted Tunneling ◽  
Working Principle

The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working principle and this analysis was compared to experimental data obtained for temperature ranging from 300 to 420 K. This methodology was performed for different nanowire diameters and bias conditions, leading to a deep investigation of parameters such as the ratio of on-state and off-state current (ION/IOFF) and the subthreshold slope (S). Three different transport mechanisms (band-to-band tunneling, Shockley-Read-Hall generation/recombination and trap-assisted tunneling) were highlighted to explain the temperature influence on the drain current. As the final step, subthreshold slope values for each configuration were compared to the room temperature. Therefore, it was observed that larger nanowire diameters and lower temperatures tended to increase ION/IOFF ratio. Meanwhile, it was clear that band-to-band tunneling prevailed for higher gate voltage bias, resulting in a much slighter temperature effect on the drain current.

scholarly journals First demonstration of robust tri-gate β-Ga2O3 nano-membrane field-effect transistors

2021 ◽  
Author(s):  
Hagyoul Bae ◽  
Tae Joon Park ◽  
Jinhyun Noh ◽  
Wonil Chung ◽  
Mengwei Si ◽  
...  
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Atomic Layer ◽  
Transfer Characteristic ◽  
Subthreshold Slope ◽  
Si Substrate ◽  
Current Voltage ◽  
First Time

Abstract Nano-membrane tri-gate β-gallium oxide (β-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β-Ga2O3 and gate dielectric, atomic layer-deposited 15-nm-thick aluminum oxide (Al2O3) was utilized with Tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV/dec, high drain current (I DS) ON/OFF ratio of 1.5 × 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current–voltage (I–V) characteristics measured at temperatures up to 400 °C.

1360 V, 5.0 mΩcm2 Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2010 ◽  
Vol 645-648 ◽  
pp. 987-990 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
Shinsuke Harada ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Field Effect ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Blocking Voltage

Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Preparation of integrated chemical sensors using commercial VLSI technology

1987 ◽  
Vol 65 (5) ◽  
pp. 1072-1078 ◽  
Author(s):  
Paul G. Glavina ◽  
D. Jed Harrison
Keyword(s):  
Chemical Sensors ◽  
Linear Response ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Microelectrode Arrays ◽  
Drain Current ◽  
Cyclic Voltammetric ◽  
Design Rules ◽  
Vlsi Technology ◽  
Commercial Technology

The fabrication of ion sensitive field effect transistors (ISFET) and microelectrode arrays for use as chemical sensors using a commercial CMOS fabrication process is described. The commercial technology is readily available through the Canadian Microelectronics Corporation; however, several of the recommended design rules must be ignored in preparing chemical sensors using this process. The ISFET devices show near theoretical response to K+ in aqueous solution (55 mV slope) when coated with a K+ sensitive membrane. An extended gate ion sensitive device is presented which offers advantages in encapsulation of ISFET sensors. The source-drain current of both devices show a linear response to log [Formula: see text] in contrast to ISFETs previously reported that have high internal lead resistances. Al and poly-Si microelectrode arrays are fabricated commercially and then Pt is electrodeposited on the microelectrodes. The resulting arrays show good cyclic voltammetric response to Fe(CN)64− and Ru(NH3)63+ and are relatively durable.

AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors (MOSHFETs) with the Delta-Doped Barrier Layer

2002 ◽  
Vol 743 ◽  
Author(s):  
Z. Y. Fan ◽  
J. Li ◽  
J. Y. Lin ◽  
H. X. Jiang ◽  
Y. Liu ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Cutoff Frequency ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Heterostructure ◽  
Heterostructure Field Effect Transistors ◽  
Gate Control

ABSTRACTThe fabrication and characterization of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with the δ-doped barrier are reported. The incorporation of the SiO2 insulated-gate and the δ-doped barrier into HFET structures reduces the gate leakage and improves the 2D channel carrier mobility. The device has a high drain-current-driving and gate-control capabilities as well as a very high gate-drain breakdown voltage of 200 V, a cutoff frequency of 15 GHz and a maximum frequency of oscillation of 34 GHz for a gate length of 1 μm. These characteristics indicate a great potential of this structure for high-power-microwave applications.

Temporal Changes in Source–Drain Current for Organic Field-Effect Transistors Caused by Dipole on Insulator Surface

2008 ◽  
Vol 1 ◽  
pp. 061801 ◽  
Author(s):  
Kouji Suemori ◽  
Misuzu Taniguchi ◽  
Sei Uemura ◽  
Manabu Yoshida ◽  
Satoshi Hoshino ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Temporal Changes ◽  
Organic Field Effect Transistors ◽  
Insulator Surface

Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels

2014 ◽  
Vol 53 (4S) ◽  
pp. 04EC11 ◽  
Author(s):  
Takashi Matsukawa ◽  
Yongxun Liu ◽  
Kazuhiko Endo ◽  
Junichi Tsukada ◽  
Hiromi Yamauchi ◽  
...  
Keyword(s):  
Work Function ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Metal Gates

scholarly journals Line-Edge Roughness from Extreme Ultraviolet Lithography to Fin-Field-Effect-Transistor: Computational Study

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1493
Author(s):  
Sang-Kon Kim
Keyword(s):  
Field Effect ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Computational Study ◽  
Drain Current ◽  
Extreme Ultraviolet Lithography ◽  
Line Edge Roughness ◽  
Stochastic Fluctuation ◽  
Ultraviolet Lithography ◽  
Edge Roughness

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.

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