Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

2014 ◽  
Vol 53 (4S) ◽  
pp. 04ED04 ◽  
Author(s):  
Takashi Ohsawa ◽  
Shoji Ikeda ◽  
Takahiro Hanyu ◽  
Hideo Ohno ◽  
Tetsuo Endoh
Keyword(s):  
Low Power ◽  
Random Access ◽  
Power Reduction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Pair Type ◽  
Power Gating ◽  
Cache Memories ◽  
Differential Pair

scholarly journals A Systematic Assessment of W-Doped CoFeB Single Free Layers for Low Power STT-MRAM Applications

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2384
Author(s):  
Siddharth Rao ◽  
Sebastien Couet ◽  
Simon Van Beek ◽  
Shreya Kundu ◽  
Shamin Houshmand Sharifi ◽  
...  
Keyword(s):  
Low Power ◽  
Nonvolatile Memory ◽  
High Speed ◽  
Random Access ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Systematic Assessment ◽  
Current Reduction ◽  
The Cost ◽  
Alternative Designs

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven the development of STT-MRAMs over the past decade, achieving data retention of 10 years at the cost of higher write power consumption. In addition, the need for tunnel magnetoresistance (TMR)-based read schemes limits the flexibility in materials beyond the typical CoFeB/MgO interfaces. In this study, we propose a novel spacerless FL stack comprised of CoFeB alloyed with heavy metals such as tungsten (W) which allows effective modulation of the magnet properties (Ms, Hk) while retaining compatibility with MgO layers. The addition of W results favours a delayed crystallization process, in turn enabling higher thermal budgets up to 180 min at 400 °C. The presence of tungsten reduces the total FL magnetization (Ms) but simultaneously increasing its temperature dependence, thus, enabling a dynamic write current reduction of ~15% at 2 ns pulse widths. Reliable operation is demonstrated with a WER of 1 ppm and endurance >1010 cycles. These results pave the way for alternative designs of STT-MRAMs for low power electronics.

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Power Gating ◽  
Scan Test

Progress and Prospects of Spin Transfer Torque Random Access Memory

2012 ◽  
Vol 48 (11) ◽  
pp. 3025-3030 ◽  
Author(s):  
E. Chen ◽  
D. Apalkov ◽  
A. Driskill-Smith ◽  
A. Khvalkovskiy ◽  
D. Lottis ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Access Memory

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

2012 ◽  
Vol 12 (4) ◽  
pp. 756-766 ◽  
Author(s):  
Charles Augustine ◽  
Niladri Narayan Mojumder ◽  
Xuanyao Fong ◽  
Sri Harsha Choday ◽  
Sang Phill Park ◽  
...  
Keyword(s):  
Low Power ◽  
Spin Transfer Torque ◽  
Spin Transfer
Sign in / Sign up

Export Citation Format

Share Document