Modeling and Analysis of Gate Line Edge Roughness Effect on CMOS Scaling Towards Deep Nanoscale Gate Length

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current (I OFF) of 0 . 03 μA/μm, and an on-current (I ON) of 1770 μA/μm, with the I ON / I OFF ratio 6 . 63 × 10 4, a value 27 % larger than that of a 10 . 7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55 . 5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.

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Modeling line edge roughness effects in sub 100 nanometer gate length devices

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) ◽

10.1109/sispad.2000.871225 ◽

2002 ◽

Cited By ~ 66

Author(s):

P. Oldiges ◽

Qimghuamg Lin ◽

K. Petrillo ◽

M. Sanchez ◽

M. Ieong ◽

...

Keyword(s):

Gate Length ◽

Line Edge Roughness ◽

Roughness Effects ◽

Edge Roughness

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Line-Edge Roughness on Fin-Field-Effect-Transistor Performance for 7-nm and 5-nm Patterns

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2020.18814 ◽

2020 ◽

Vol 20 (11) ◽

pp. 6912-6915

Author(s):

Sang-Kon Kim

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

Critical Dimension ◽

Critical Issue ◽

Gate Length ◽

Line Edge Roughness ◽

Stochastic Fluctuation ◽

Edge Roughness ◽

Electric Potentials ◽

The Impact

The line-edge roughness (LER) is a critical issue that significantly impacts the critical dimension (CD) because the LER does not scale with the feature size. Hence, the LER influences the device performance with 7-nm and 5-nm patterns. In this study, LER impact on the performance of the fin-field-effect-transistors (FinFETs) are investigated using a compact device method. The fin-width roughness (FWR) is based on the stochastic fluctuation such as the LER and the line-width roughness (LWR) in the lithography process. The calculated results of the FWRs and the gate lengths L = 7-nm and 5-nm are addressed with the cases of electric potentials with the y-direction along the gate length, electric potentials with the x-direction along the fin width, and the absolute drain currents with the gate lengths L = 7-nm or 5-nm due to gate voltages. According to the gate length, the impact of the FWR patterns on the performance of fin-field-effect-transistors (FinFETs) can find regular fluctuations.

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