scholarly journals Die Crack Resolution through Pick-up Process Optimization for BGA Package

Author(s):  
R. Rodriguez ◽  
E. Graycochea Jr. ◽  
F. R. Gomez ◽  
E. Manalo

With the new devices and new technologies in the semiconductor industry are getting more challenging to process because issues are unavoidable especially on thin dies. The paper is focused on the improvement done on a ball grid array (BGA) substrate package assembly to address the quantity of rejection of die crack during die picking at the die attach process station. High pick force and high needle top height found out during the pick-up process is the main root cause of die crack. Parameter optimization particularly for die picking with the combination of pick force and needle top height parameter was done to eliminate this type of issue after the die attaches process. With the die attach process improvement, a reduction of 100 percent of die crack occurrence was successfully achieved. For future works, the improvement and learnings could be used for devices with similar constraints.

Author(s):  
Antonio R. Sumagpang Jr. ◽  
Frederick Ray I. Gomez ◽  
Edwin M. Graycochea Jr.

With the new devices and new technologies in semiconductor industry are getting more challenging to process because of new processes and process bricks. One of the most challenging assembly processes is the pick and place or the die attach process. Issues were encountered during product development phase of a semiconductor ball grid array (BGA) device of radio frequency (RF) applications and one of which is the “thrown” dies during die picking. This paper is focused on addressing the thrown dies issue at pick and place process. Installation of blower ionizer on the machine is an extensive improvement done to eliminate the foreign materials resulting to thrown dies during picking. With this improvement, a reduction of around 80 percent of thrown dies was achieved. For future works, the improvement and learnings could be used for devices with similar requirement.


Author(s):  
Edwin M. Graycochea Jr. ◽  
Endalicio D. Manalo ◽  
Rennier S. Rodriguez ◽  
Frederick Ray I. Gomez

The paper is focused on the glue voids reduction on critical semiconductor quad-flat no-leads (QFN) device processed on a stencil printing type of die attach machine. Process optimization through material preparation improvement was done to mitigate the silver lumps of the sintering glue which is a main contributor on the voids occurrence. Eventually, the glue voids were reduced to less than the allowed 5% limit. For future works, the learnings and configuration could be used on devices with similar requirement.


2000 ◽  
Vol 123 (1) ◽  
pp. 88-94 ◽  
Author(s):  
Takashi Aihara ◽  
Shingo Ito ◽  
Hideaki Sasajima ◽  
Ken Oota

The market for BGA packages is expanding all over the world, owing to the ease of its mounting onto the PC boards. On the other hand, BGA packages possess certain shortcomings compared to QFPs. Anti-solder crack performance on Fine Pitch BGA (=FPBGA) and warpage on Mold Array Package-BGA(=MAP-BGA) are significant disadvantages. To improve the performance of BGA packages, we studied various combinations of materials used for BGA package including molding compounds, die attach pastes, and substrates.


Author(s):  
Rennier S. Rodriguez ◽  
Frederick Ray I. Gomez

Nowadays, electronic manufacturers trend are to become thinner and thinner especially those electronic gadgets that is very handy and convenient on our daily necessity. Challenge with the leading manufacturers is the production and development of less size gadget yet with richness of available application and uses that we can work on with what can please its consumer for their convenience and satisfaction. As with the semiconductor company, correlation between becoming thinner versus manufacturing capability become significantly opposite, as the package become thinner the more complex its related process can be. This study covers innovative approach in die attach station on critical handling of thin die packages. Lessons and learning were documented from Ball Grid Array (BGA) packages as first to be evaluated with thin package requirements.  Also discussed herewith are documented defects and related issues during trials and die attach builds that has been a show stopper on its early production.


Author(s):  
Bryan Christian Bacquian ◽  
Frederick Ray Gomez

The semiconductor industry is becoming more inclined to thinner integrated circuit (IC) packages. Thinner packages with thin wafer or die prefer the die attach film (DAF) technology as the die adhesive material solution. As the wafer goes thinner, it becomes more of a challenge in process development, especially during its assembly preparatory stages. As the dies become smaller and thinner, wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality. New technologies were developed and introduced in the industry and one of this is the laser die attach film (DAF) cutting. The method was developed together with dies before grinding (DBG) as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw. This paper discusses the laser DAF cut development covering the design of experiments (DOE) to understand the different characteristics of laser DAF solution. Validations are made through actual simulation and wafer processing. The paper also covers the interaction of different DAF thicknesses and parameters in order to define the critical characteristics in achieving optimal DAF cutting process responses.


Author(s):  
Rennier Rodriguez ◽  
Jr. Edwin Graycochea ◽  
Frederick Ray Gomez

Die placement reference in die attach process is one of the critical aspects in measuring the actual die placement especially for the device that has a required measurement. This paper focused on the re-design on the layout of the substrate ball grid array (BGA) package with cross fiducials at the singulation lane which are located at the corner portions of the device. The cross fiducial would serve as a reference when measuring the actual placement of the Silicon die in the package. With this improvement, the technicians and operators could now easily identify the reference based on the mount and bonding diagram requirement.


Author(s):  
Jonathan Pulido ◽  
Frederick Ray Gomez ◽  
Edwin Graycochea Jr.

With the continuous trend of new technologies in semiconductor manufacturing assembly, challenges and issues are unavoidable. This paper presents an improvement done in quad-flat no-leads (QFN) leadframe package to resolve the quantity of unit rejection due to leads scratch underneath the leadframe. Moreover, the reject manifestation was captured after wirebonding process. Parameter optimization particularly for the second bond with the combination of bond force and bond scrubbing parameters was done to totally eliminate this type of issue after wirebonding process. With the wirebonding process optimization and improvement done, a reduction of 95 percent of leads scratch occurrence was achieved.


Author(s):  
Antonio R. Sumagpang Jr. ◽  
Edwin M. Graycochea Jr. ◽  
Frederick Ray I. Gomez

With the new and upcoming technologies in semiconductor industry, packages like the ball grid array (BGA) are getting more challenging to process due to inherent issues that come along. Process improvement through modification in the design of indirect material is one key direction to improve the productivity during assembly manufacturing. In this paper, an enhanced design of dipping plate is presented to solve the issue of flux shorting due to out-of-specs dipping plate at ball attach process. The study used a side by side comparison to prove that the new design  is better than that of the out-of-specs indirect material. With the new enhanced design of  dipping plate and the optimized flux depth parameter, flux shorting occurrence was successfully mitigated.


Author(s):  
Bryan Christian S. Bacquian ◽  
Edwin M. Graycochea Jr. ◽  
Frederick Ray I. Gomez

The development of new technology with thinner and smaller packages has become the movement and focus on semiconductor assembly industry. This paper presents an improvement done in dual-flat no-leads (DFN) package to resolve the quantity of rejection due to die attach film (DAF) bleed out on the die paddle of the leadframe. This reject manifestation was seen after die attach process. Parameter optimization particularly for the bonding with the combination of bond force and bond time parameter was done to eliminate this type of issue after die attach process. With this die attach process optimization and improvement done, DAF bleed out occurrence was eliminated with 100% reduction improvement.


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