Deep depletion capacitance–voltage technique for spatial distribution of traps across the substrate in MOS structures

2020 ◽  
Vol 173 ◽  
pp. 107905
Author(s):  
Han Bin Yoo ◽  
Jintae Yu ◽  
Haesung Kim ◽  
Ji Hee Ryu ◽  
Sung-Jin Choi ◽  
...  
Keyword(s):  
Spatial Distribution ◽  
Capacitance Voltage ◽  
Mos Structures

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

Electrical Characterization of Al2O3 - SiO2 Mos Structures

1999 ◽  
Vol 567 ◽  
Author(s):  
L-Å Ragnarsson ◽  
E. Aderstedt ◽  
P. Lundgren
Keyword(s):  
Electrical Characterization ◽  
Thickness Reduction ◽  
Initial Thickness ◽  
Equivalent Thickness ◽  
Conventional Furnace ◽  
Capacitance Voltage ◽  
Layered Dielectric ◽  
The Impact ◽  
Mos Structures

ABSTRACTA comparative capacitance voltage method is used to investigate the equivalent thickness reduction during post metallization annealing of thermally grown ultrathin (∼15-27 Å) oxides. It is found that a double layered dielectric consisting of a thin Al2O3—SiO2 sandwich is appropriate to describe both the increased capacitance and the nearly unaltered current after anneal. It is further shown that the impact of initial thickness and method of growth — in a conventional furnace or by rapid thermal oxidation — on the equivalent thickness reduction is negligible.

Characterization of SiC MOS Structures using Conductance Spectroscopy and Capacitance Voltage Analysis

2000 ◽  
Vol 338-342 ◽  
pp. 1117-1120 ◽  
Author(s):  
Einar Ö. Sveinbjörnsson ◽  
M. Ahnoff ◽  
H.Ö. Ólafsson
Keyword(s):  
Capacitance Voltage ◽  
Mos Structures

Electrical Properties of Metal-Oxide-Semiconductor (MOS) Structures on 4H-SiC(0001) Formed by Oxidizing Pre-Deposited SixNy

2007 ◽  
Vol 556-557 ◽  
pp. 647-650 ◽  
Author(s):  
Jeong Hyun Moon ◽  
Dong Hwan Kim ◽  
Ho Keun Song ◽  
Jeong Hyuk Yim ◽  
Wook Bahng ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Metal Oxide ◽  
Current Density ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Field ◽  
Mos Capacitors ◽  
Dielectric Layers ◽  
Capacitance Voltage ◽  
Mos Structures

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with ultra thin (5 nm) remote-PECVD SixNy dielectric layers and investigated electrical properties of nitrided SiO2/4H-SiC interface after oxidizing the SixNy in dry oxygen at 1150 °C for 30, 60, 90 min. Improvements of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements in comparison with dry oxide. The improvements of SiC MOS capacitors formed by oxidizing the pre-deposited SixNy have been explained in this paper.

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Effects of Arsenic Segregation and Electron Trapping on the Capacitance-Voltage Behavior of Polysilicon and Polycide Gates

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Lin ◽  
S. Batra ◽  
K. Park ◽  
J. Lee ◽  
S. Banerjee ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Electron Trapping ◽  
Dopant Segregation ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Capacitance Voltage ◽  
Higher Temperature ◽  
Amorphous Si ◽  
Mos Structures ◽  
Mos Device

AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

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