Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors

The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.

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Simulation of the Nanoscale Joint Surrounding Gate SOI MOSFET Characteristics

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.k7831.1091220 ◽

2020 ◽

Vol 9 (12) ◽

pp. 150-153

Keyword(s):

High Performance ◽

Low Voltage ◽

Supply Voltage ◽

High Gain ◽

Power Supply Voltage ◽

Short Channel ◽

Work Area ◽

Strong Inversion ◽

Surrounding Gate ◽

Common Gate

In order to solve the current problem of increasing the efficiency of modern electronic circuits, the applicability of a nanoscale joint surrounding gate MOSFET with oval work area is discussed. The design and principle of its operation are considered. This concept involves of jointing the working areas of n-channel and p-channel MOSFETs. In fact, the JSMOSFET consists of two "glued" along the halves of MOSFETs: one - nchannel and the other - p-channel, but with one common gate. We analyze the applicability of the design of an oval-shaped protected area. In our case, the contact of two heterogeneously doped regions occurs in the plane passing through the small axis of the oval. The main channels are formed in zones associated with the large axis of the oval. This achieves the main goalincreasing the number of charge carriers. At the same time, the efficiency of short-channel effect suppression is maintained and a high current level of the transistor is provided in the strong inversion mode. By the developed TCAD model of a nanoscale joint surrounding gate MOSFET with an oval work area the electrophysical characteristics of several prototypes with different transverse dimensions were numerically calculated at a supply voltage of 0.5 V. From the simulation results, it follows that all prototypes are low-voltage devices that can function at voltages below 0.5 V in the gigahertz frequency range with a high gain. The proposed devices perform the function of inverting the input signal without distortion. From the comparison of modeling data, the scope scaling capabilities are determined. The obtained results create prerequisites for the development of the proposed transistor architecture, since electronic chips created on their basis will differ in low power supply voltage, high performance, and minimal occupied area, which meets modern requirements for transistors for analog and digital applications.

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Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

Nano- i Mikrosistemnaya Tehnika ◽

10.17587/nmst.23.75-82 ◽

2021 ◽

Vol 23 (2) ◽

pp. 75-82

Author(s):

Masalsky N.V. ◽

Keyword(s):

Low Voltage ◽

Supply Voltage ◽

Logic Gates ◽

Active Power ◽

Short Channel Effects ◽

Short Channel ◽

Switching Delay ◽

Surrounding Gate ◽

Channel Effects ◽

Soi Cmos

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

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A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

International Journal of Engineering Research in Africa ◽

10.4028/www.scientific.net/jera.19.19 ◽

2015 ◽

Vol 19 ◽

pp. 19-36 ◽

Cited By ~ 2

Author(s):

P.A. Gowri Sankar ◽

G. Sathiyabama

Keyword(s):

Power Consumption ◽

Low Power ◽

Circuit Design ◽

Field Effect ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Technology ◽

Flash Adc ◽

Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

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Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

VLSI Design ◽

10.1155/2012/173079 ◽

2012 ◽

Vol 2012 ◽

pp. 1-18 ◽

Cited By ~ 13

Author(s):

Subodh Wairya ◽

Rajendra Kumar Nagaria ◽

Sudarshan Tiwari

Keyword(s):

High Speed ◽

High Performance ◽

Low Voltage ◽

Supply Voltage ◽

Vlsi Design ◽

Reducing Power ◽

Full Adder ◽

Process Models ◽

Majority Function ◽

Simulation Results

This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC 0.18 m process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

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Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

npj 2D Materials and Applications ◽

10.1038/s41699-021-00280-7 ◽

2022 ◽

Vol 6 (1) ◽

Author(s):

Taikyu Kim ◽

Cheol Hee Choi ◽

Pilgyu Byeon ◽

Miso Lee ◽

Aeran Song ◽

...

Keyword(s):

Field Effect ◽

Physical Vapor Deposition ◽

High Performance ◽

Supply Voltage ◽

Field Effect Transistors ◽

Low Cost ◽

Three Dimensional ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

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Low Power based Dynamic TSPC D flip flop for High Performance Applications

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.h6666.069820 ◽

2020 ◽

Vol 9 (8) ◽

pp. 758-762

Keyword(s):

Low Power ◽

Field Effect ◽

High Performance ◽

Field Effect Transistor ◽

Memory Cell ◽

Research Center ◽

Short Channel ◽

Flip Flop ◽

Force Application ◽

Effect Transistor

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

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CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156406003618 ◽

2006 ◽

Vol 16 (01) ◽

pp. 193-219 ◽

Cited By ~ 1

Author(s):

S. DELEONIBUS ◽

B. de SALVO ◽

T. ERNST ◽

O. FAYNOT ◽

T. POIROUX ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Gate Dielectric ◽

Low Voltage ◽

Short Channel Effects ◽

Short Channel ◽

Trade Offs ◽

Future System ◽

The Future ◽

Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

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High-Performance Low Voltage Organic Thin-Film Transistors

MRS Proceedings ◽

10.1557/proc-870-h1.4 ◽

2005 ◽

Vol 870 ◽

Cited By ~ 5

Author(s):

Stijn De Vusser ◽

Soeren Steudel ◽

Kris Myny ◽

Jan Genoe ◽

Paul Heremans

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

High Performance ◽

Low Voltage ◽

Supply Voltage ◽

Organic Thin Film Transistors ◽

Ring Oscillator ◽

Ring Oscillators ◽

Organic Thin Film ◽

Supply Voltages

AbstractIn this work, we report on high-performance low voltage pentacene Organic Thin-Film Transistors (OTFT's) and circuits. Inverters and ring oscillators have been designed and fabricated. At 15 V supply voltage, we have observed invertors showing a voltage gain of 9 and an output swing of more than 13 V. As for the ring oscillators, oscillations started at supply voltages as low as 8.5 V. At a supply voltage of only 15 V, a stage delay time of 3.3 νs is calculated from experimental results.We believe that these results show for the first time a high speed ring oscillator at relatively low supply voltages. The required supply voltages can be obtained by rectification using an organic (pentacene) diode. These results may have an important impact on the realization of RF-ID tags: by integrating our circuits with an organic diode, the fabrication of organic RF-ID tags comes closer.

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