Development of UV Curable Wafer Back Side Protection-Film for Wafer Level Chip Size Package

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 ï¬m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

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Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2015dpc-tp31 ◽

2015 ◽

Vol 2015 (DPC) ◽

pp. 000698-000725 ◽

Cited By ~ 1

Author(s):

Kai Zoschke ◽

Klaus-Dieter Lang

Keyword(s):

Wafer Bonding ◽

Rf Mems ◽

Electrical Contacts ◽

Bonding Process ◽

Frame Structure ◽

Back Side ◽

Wafer Level ◽

Free Standing ◽

Carrier Wafer ◽

Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

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Solder Joint Reliability Study for Wafer Level Packages on Flexible and Rigid Boards

International Symposium on Microelectronics ◽

10.4071/isom-2013-ta22 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000039-000044

Author(s):

Gary Gu ◽

Jon Chadwick ◽

Daniel Jin

Keyword(s):

Solder Joint ◽

Parametric Design ◽

Low Cost ◽

Wafer Level ◽

Solder Joint Reliability ◽

Conformal Coating ◽

Joint Reliability ◽

Chip Size ◽

The Right ◽

Elastic Plastic Materials

Applications of Wafer Level Packages (WLPs) have shown tremendous growth in the rapid developing smartphones and other portable electronic devices. The technology trends lead to smaller chip size, low cost, and more integrated functions, but also face higher reliability requirements due to the reduced number of solder bumps as well as smaller bump size and height. New assembly technologies such as flexible phone board and conformal coating also brought up new thermo-mechanical reliability challenges. Based on 3D finite element modeling, the current studies focus on solder joint reliability of WLPs and compared between flex based and traditional rigid based WLP assemblies. Conformal coated and underfilled WLPs as well as some bump parameters are also studied. The parametric studies were carried out in ANSYS and all models were created by using APDL (ANSYS Parametric Design Language) scripts. Each simulation starts from stress free status set at solder reflow temperature and were subjected to thermal cyclic load between −40 and +125°C with ramp and dwell time. Creep strain was considered for solder alloys and kinematic plastic hardening was considered for other elastic-plastic materials. The solder fatigue life is estimated by using modified Coffin-Manson equation and was compared with available thermal cycling test data. The results show that underfill is still the most effective option and conformal coating can play an important role if the right material is selected. Bump parameters such as height, which have certain effects on the solder reliability on WLP-on-Rigid, have limited impact on WLP-on-Flex assembly.

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Reliability Study of Reference Semiconductor Encapsulation Materials for Biocompatible Packaging

International Symposium on Microelectronics ◽

10.4071/isom-2012-ta51 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000148-000153

Author(s):

Karl Malachowski ◽

Karen Qian ◽

Maaike Op de Beeck ◽

Rita Verbeeck ◽

George Bryce ◽

...

Keyword(s):

Elevated Temperatures ◽

Process Integration ◽

Material Selection ◽

Semiconductor Industry ◽

Electrical Performance ◽

Integration Scheme ◽

Back Side ◽

Wafer Level ◽

Nitride Layers

Material selection is the key issue when developing a biocompatible packaging process for implantable electronic systems. To secure a reliable performance of the chip in such a package, its encapsulation has to be considered up-front in the wafer-level integration scheme. A differentiation of two main material types can be made:1) Insulating or passive materials functioning as a bi-directional diffusion barrier preventing body fluids leaking into the package causing systems malfunction due to possible materials corrosion and also avoiding a leakage of built-in materials to the in-vivo environment and2) Conductive or active materials as diffusion barriers, e.g. against copper diffusion or as direct external contacts responsible for electrical performance of the system. This study investigates the properties of two widely used insulating materials in the semiconductor industry, the nitride and the oxide. Both material types are deposited in a PECVD system using different temperatures; 400 ° C for CMOS compatibility and 200 ° C for wafer back side process integration when a temporary carrier system is used. The biocompatibility investigations of these materials (evaluated using cell lines and primary cells) show promising results. However, for the long term application, the stability results for the oxide layers show hydration effects resulting in material degradation where the nitride layers clearly show corrosion and are even etched when elevated temperatures are applied. This fact is surprising since nitride layers are widely used as a humidity barrier for various chip types but obviously not suitable for a direct contact with liquids. Various analysis methods using e.g. Fourier Transformed IR Spectroscopy or mass measurements substantiate this thesis.

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A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

Electronics ◽

10.3390/electronics9081210 ◽

2020 ◽

Vol 9 (8) ◽

pp. 1210

Author(s):

Hanh Dang-ba ◽

Gyung-su Byun

Keyword(s):

Wireless Power Transfer ◽

Cmos Technology ◽

Power Delivery ◽

Transfer Efficiency ◽

Power Transfer ◽

Wireless Power ◽

Wafer Level ◽

Power Transfer Efficiency ◽

Chip Size ◽

On Chip

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

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MEMS-CMOS Integrated Tactile Sensor with Digital Signal Processing for Robot Application

MRS Proceedings ◽

10.1557/opl.2012.1489 ◽

2012 ◽

Vol 1427 ◽

Cited By ~ 1

Author(s):

M. Makihata ◽

M. Muroyama ◽

S. Tanaka ◽

H. Yamada ◽

T. Nakayama ◽

...

Keyword(s):

Signal Processing ◽

Digital Signal ◽

Tactile Sensor ◽

Force Sensor ◽

Digital Data ◽

Wafer Level ◽

Tactile Sensors ◽

Low Profile ◽

Chip Size ◽

Tactile Receptor

ABSTRACTAn ultra-small tactile sensor with functions of signal processing and digital communication has been prototyped based on MEMS-CMOS integration technology. The designed analog-digital mixed signal ASIC allows many tactile sensors to connect each other on a common bus line, which drastically reduces the number of wire. The ASIC capacitively detects the deformation of a force sensor and sends digital data to the common bus line when the force exceeds a threshold. The digital data contain a physical ID of each sensor, 32-bit sensing data and 16-bit cyclic redundancy check (CRC) code. In this study, a novel wafer-level integration and packaging technology were developed, and a chip-size-packaged tactile sensor with a small footprint (2.5mm×2.5mm) and a low profile (0.27mm) was prototyped and tested. The sensor autonomously sends digital data like a tactile receptor of human.

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