scholarly journals A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1773
Author(s):  
Yunrui Zhao ◽  
Zhiming Chen ◽  
Zicheng Liu ◽  
Xiaoran Li ◽  
Xinghua Wang
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Single Phase ◽  
Frequency Synthesizer ◽  
Operating Frequency ◽  
Low Power Consumption ◽  
Reference Frequency ◽  
Frequency Range ◽  
Flip Flop ◽  
Pll Frequency Synthesizer

High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.

Design of Broadband, High-Speed Dual-Modulus Prescaler for Multi-Mode PLL Frequency Synthesizer

2013 ◽  
Vol 364 ◽  
pp. 439-443
Author(s):  
Xue Fei Jiang ◽  
Xiang Ning Fan
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Frequency Synthesizer ◽  
Cmos Technology ◽  
Frequency Range ◽  
Dual Mode ◽  
Hardware Cost ◽  
Operating Frequency Range ◽  
Pll Frequency Synthesizer ◽  
Multi Mode

A architecture of multi-mode PLL frequency synthesizer one can meet a variety of communication standards is presented in this paper, which can provide each mode with the required frequency, while reducing the system's hardware cost. Optimized broadband high-speed dual-mode prescaler (DMP)'s internal structure, the principle of circuit design and its layout is introduced. The DMP is produced by 0.18μm CMOS technology. The post simulation results show that with the 1.8V power, the DMP's operating frequency range is 0.4 ~ 9.6GHz, the power consumption is 7.6mA.

A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks

2015 ◽  
Vol 24 (07) ◽  
pp. 1550109
Author(s):  
Meilin Wan ◽  
Zhenzhen Zhang ◽  
Wang Liao ◽  
Kui Dai ◽  
Xuecheng Zou
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Single Phase ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Low Power Consumption ◽  
Frequency Range ◽  
Differential Input ◽  
Operating Frequency Range ◽  
Simulation Results

A dual-modulus prescaler (divide-by-2/3) using complementary clocking NMOS-like blocks is presented in this paper. The prescaler can work properly for both differential and single phase input clocks. For differential input clocks, the prescaler achieves not only high operating frequency but also low power consumption since it consists of only five NMOS-like blocks. For single phase input clock, the operating frequency range is further expanded by utilizing a complementary clocks generator. Simulation results show that, in 180-nm standard CMOS technology, the proposed prescaler achieves operating frequency range of 1.7–9.0 GHz for differential input clocks and 0.5–10.2 GHz for single phase input clock. And the maximum power consumption from 1.8 V power supply is 0.92 mW and 1.32 mW for differential and single phase input clocks respectively.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Implementation of time efficient hybrid multiplier for FFT computation

2018 ◽  
Vol 7 (2.7) ◽  
pp. 409 ◽  
Author(s):  
R Nikhil ◽  
G V. S. Veerendra ◽  
J Rahul M. S. Sri Harsha ◽  
Dr V. S. V. Prabhakar
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Chip Area ◽  
Booth Multiplier ◽  
Low Delay ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.  

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

A Novel Design of high performance low power phase frequency Detector for CMOS PLL frequency Synthesizer

2019 ◽  
Vol 09 ◽  
Author(s):  
Monika Bhardwaj ◽  
Sujata Pandey ◽  
Neeta Pandey
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Operating Frequency ◽  
Feedback Signal ◽  
Input Frequency ◽  
Phase Frequency Detector ◽  
Pll Frequency Synthesizer ◽  
Frequency Detector

Aims: A high performance low power phase frequency detector is designed and simulated. The various different parameters of the circuit are obtained through various type of simulations. We worked mainly upon the power dissipation, power supply, input frequency range and its area. The proposed PFD will have the locking capability i.e. to lock at the edges either on the rising or falling edge w.r.t the reference and the feedback signal. The proposed design will have the very high performance and ultra-low phase noise. It has the added advantage of low cost and the compact size. Objective: The primary objective is to design a low power phase frequency detector for CMOS PLL Frequency Synthesizer using lows power technique. Method: The pass transistor logic is used in the circuit to eliminate the reset path. By this change of the path the operating frequency and operating speed both are increased in the proposed design. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD design will have a less number of transistors and also a low consumption of power. The output pulses of the PFD at phase difference of 0, 0,п/2, п, 3п/2, 2п will have its average voltage as 0, VDD and VDD/2. The proposed phase detector will perfectly detect the phase difference between two signals so that the harmonics problem can be minimized. Result: The proposed design is having its operating frequency as 5GHz over the conventional one which has its frequency as 800MHz. Power dissipation in the proposed design is reduced due to less number of transistors used as compared with the conventional one. The operating region has become much wider for proposed design as it is having operating frequency much higher than that of the conventional one. Conclusion: The proposed PFD will increase the locking capability on the both rise and fall edge w.r.t. the reference and the feedback signal. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD circuit will have a less number of transistors and also a low consumption of power 7.14 mW.

scholarly journals Review of high-speed phase accumulator for direct digital frequency synthesizer

2020 ◽  
Vol 10 (4) ◽  
pp. 4008
Author(s):  
Abdulkareem Dawah Abbas
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Frequency Control ◽  
Control Word ◽  
Description Language ◽  
Flip Flop ◽  
Ripple Carry Adder ◽  
Field Programmable ◽  
Hardware Description ◽  
Prefix Adders

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

scholarly journals A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2494
Author(s):  
Lu Tang ◽  
Kuidong Chen ◽  
Youming Zhang ◽  
Xusheng Tang ◽  
Changchun Zhang
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Frequency Divider ◽  
Flip Flop ◽  
Ka Band ◽  
Locking Range ◽  
Type Frequency ◽  
Operation Frequency ◽  
Programmable Frequency Divider

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

1996 ◽  
Vol 31 (9) ◽  
pp. 1361-1363 ◽  
Author(s):  
T. Maeda ◽  
K. Numata ◽  
M. Fujii ◽  
M. Tokushima ◽  
S. Wada ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Power Consumption ◽  
Flip Flop ◽  
Ultra Low Power
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