A Novel Design of high performance low power phase frequency Detector for CMOS PLL frequency Synthesizer

2019 ◽  
Vol 09 ◽  
Author(s):  
Monika Bhardwaj ◽  
Sujata Pandey ◽  
Neeta Pandey
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Operating Frequency ◽  
Feedback Signal ◽  
Input Frequency ◽  
Phase Frequency Detector ◽  
Pll Frequency Synthesizer ◽  
Frequency Detector

Aims: A high performance low power phase frequency detector is designed and simulated. The various different parameters of the circuit are obtained through various type of simulations. We worked mainly upon the power dissipation, power supply, input frequency range and its area. The proposed PFD will have the locking capability i.e. to lock at the edges either on the rising or falling edge w.r.t the reference and the feedback signal. The proposed design will have the very high performance and ultra-low phase noise. It has the added advantage of low cost and the compact size. Objective: The primary objective is to design a low power phase frequency detector for CMOS PLL Frequency Synthesizer using lows power technique. Method: The pass transistor logic is used in the circuit to eliminate the reset path. By this change of the path the operating frequency and operating speed both are increased in the proposed design. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD design will have a less number of transistors and also a low consumption of power. The output pulses of the PFD at phase difference of 0, 0,п/2, п, 3п/2, 2п will have its average voltage as 0, VDD and VDD/2. The proposed phase detector will perfectly detect the phase difference between two signals so that the harmonics problem can be minimized. Result: The proposed design is having its operating frequency as 5GHz over the conventional one which has its frequency as 800MHz. Power dissipation in the proposed design is reduced due to less number of transistors used as compared with the conventional one. The operating region has become much wider for proposed design as it is having operating frequency much higher than that of the conventional one. Conclusion: The proposed PFD will increase the locking capability on the both rise and fall edge w.r.t. the reference and the feedback signal. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD circuit will have a less number of transistors and also a low consumption of power 7.14 mW.

PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

2020 ◽  
Vol 13 (4) ◽  
pp. 516-530
Author(s):  
Suraj K. Saw ◽  
Madhusudan Maiti ◽  
Preetisudha Meher ◽  
Alak Majumder
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Dead Zone ◽  
Cmos Technology ◽  
Switching Noise ◽  
Phase Frequency Detector ◽  
Layout Area ◽  
Frequency Detector ◽  
Lock In

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors. Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V. Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

A low power fast-settling frequency-presetting PLL frequency synthesizer

2010 ◽  
Vol 31 (8) ◽  
pp. 085002 ◽  
Author(s):  
Geng Zhiqing ◽  
Yan Xiaozhou ◽  
Lou Wenfeng ◽  
Feng Peng ◽  
Wu Nanjian
Keyword(s):  
Low Power ◽  
Frequency Synthesizer ◽  
Pll Frequency Synthesizer ◽  
Fast Settling

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

scholarly journals Design and Implementation of Low Power Delay Locked Loop using Multiplexer Based Phase Frequency Detector

2020 ◽  
Vol 9 (5) ◽  
pp. 951-955
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Clock Recovery ◽  
Clock Frequency ◽  
Phase Frequency Detector ◽  
Delay Locked Loop ◽  
Design And Implementation ◽  
Frequency Detector

This paper proposes design and implementation of low power Delay Locked Loop Architecture, with dynamic Multiplexer based Phase Frequency Detector with minimum locking time. Clock and data recovery systems are employed to derive the clocking information to correctly decode the transmitted data at the receiver. Delay Locked Loop is one of the most important clock recovery systems. The DLL architecture is designed using Cadence Virtuoso 180nm Technology with 1.8V power supply. The proposed DLL with Multiplexer based phase frequency detector shows significant reduction in power dissipation by 10% compared to DLL designed using D-FF based PFD and achieves locking state within 10 clock cycles with minimum jitter of 4.84326ps, measured within clock frequency range of 100-250MHz.

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