Power Optimization in Domino Circuits Using Current Mirror Based Leakage Compensating Keeper

2014 ◽  
Vol 573 ◽  
pp. 169-175
Author(s):  
P. Karthikeyan ◽  
R. Saravanan ◽  
N. Saravanan
Keyword(s):  
Noise Immunity ◽  
Power Reduction ◽  
Current Mirror ◽  
Speed Reduction ◽  
Low Leakage ◽  
Domino Circuit ◽  
Capacitance Current ◽  
Domino Circuits ◽  
Or Gate ◽  
Address Decoders

In this work low leakage and high noise immunity domino circuit with negligible speed degradation is proposed. Wide Fan-In Gates are widely used as address decoders in memories. Wide Fan-In Gates increase the capacitance of the dynamic node which reduces the speed in domino circuits. Current contention exists between keeper transistor and evaluation network adding to speed reduction. To overcome this problem logic implementation network in the proposed Leakage Compensating Keeper (LCK) is separated from the dynamic node by current comparison stage in which the current of the pull up network is used to charge the capacitor at the dynamic node. Since capacitance is reduced the loss in speed due to additional transistors is compensated. Because of reduced parasitic capacitance Current Mirror based LCK is enough to design faster circuits. LCK improves the noise immunity by grounding the pull up networks leakage current. Simulation results shows that the proposed circuit has 22% power reduction compared to Standard Footless Domino for a 64bit input OR gate.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals Noise measurement in high-speed domino pseudo-CMOS keeper

2018 ◽  
Vol 52 (1-2) ◽  
pp. 20-27
Author(s):  
R Jaikumar ◽  
P Poongodi
Keyword(s):  
Low Power ◽  
High Speed ◽  
Noise Immunity ◽  
Delay Reduction ◽  
Power Dynamic ◽  
Unity Noise Gain ◽  
Power Delay Product ◽  
The Cost ◽  
Domino Circuits ◽  
Or Gate

Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

Sleep signal controlled footless domino circuit for low leakage current

Circuit World ◽  
2018 ◽  
Vol 44 (2) ◽  
pp. 87-98
Author(s):  
Amit Kumar Pandey ◽  
Tarun Kumar Gupta ◽  
Pawan Kumar Verma
Keyword(s):  
Power Consumption ◽  
Threshold Voltage ◽  
Leakage Power ◽  
Content Type ◽  
Control Techniques ◽  
Low Leakage ◽  
Domino Circuit ◽  
Dual Threshold Voltage ◽  
Domino Circuits ◽  
Sleep Control

Purpose This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents. Design/methodology/approach In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state. Findings The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits. Originality/value The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

2015 ◽  
Vol 24 (05) ◽  
pp. 1550073 ◽  
Author(s):  
Vikas Mahor ◽  
Manisha Pattanaik
Keyword(s):  
High Speed ◽  
Noise Immunity ◽  
Logic Gate ◽  
Dynamic Logic ◽  
Critical Issue ◽  
Low Noise ◽  
Back Gate ◽  
High Noise ◽  
Low Leakage ◽  
Or Gate

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

A Modified High Speed Domino with Low Leakage for Wide Fan-in Domino OR-Gate

2018 ◽  
Author(s):  
Ankur Kumar ◽  
Vikrant Varshney ◽  
Pratosh Kumar Pal ◽  
R. K. Nagaria ◽  
Avaneesh Kumar Dubey
Keyword(s):  
High Speed ◽  
Low Leakage ◽  
Or Gate

scholarly journals Long Channel Keeper Based Open Loop Difference Amplifier Domino For Noise Tolerant Low Power Or Gates

2019 ◽  
Vol 8 (10) ◽  
pp. 3331-3340
Keyword(s):  
Power Consumption ◽  
Noise Immunity ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Open Loop ◽  
High Input ◽  
Noise Tolerant ◽  
Capacitive Loading ◽  
Long Channel ◽  
Or Gate

This paper proposes an open loop difference amplifier with long channel keeper technique for domino logic circuits implemented as wide fan in OR gate. Currently OR gates suffer from high capacitive loading and delays due to such loading. The proposed design uses single stage of comparison and dual keeper arrangement to generate and hold the output logic state. This technique effectively reduces the high input loading from capacitance and manages the power consumption by switching based on the generated difference voltage. As compared to standard footerless domino SFLD, the proposed design OLDA has shown to reduce power consumption by 42% in 64 bit configuration. It has increased average noise immunity by 2.03 times, while maintaining same speed as compared to SFLD. All simulations are done in CMOS technology with 90nm PTM LP models

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

2020 ◽  
Vol 12 ◽  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Ajay Kumar ◽  
Brahamdeo Prasad Singh
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Efficiency ◽  
Dynamic Logic ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage ◽  
Dynamic Circuits ◽  
Power Delay Product ◽  
Domino Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

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