Mechanical and Thermal Board Level Reliability Comparison Between Electroless Ni Im. Au and Solder on Pad Surface Finishes for Large Flip Chip BGA Packages

2006 ◽  
Author(s):  
Gnyaneshwar Ramakrishna ◽  
Donghyun Kim ◽  
Mudasir Ahamad ◽  
Lavanya Gopalakrishnan ◽  
Mason Hu ◽  
...  
Keyword(s):  
Surface Finish ◽  
Flip Chip ◽  
High Reliability ◽  
Electroless Nickel ◽  
Temperature Cycling ◽  
Design Parameters ◽  
Temperature Cycle ◽  
Bga Packages ◽  
Reliability And Robustness ◽  
Board Level

Large Flip Chip BGA (FCBGA) packages are needed in high pin out applications (>1800), e.g., ASIC's and are typically used in high reliability and robustness applications. Hence understanding the package reliability and robustness becomes one of paramount importance for efficient product design. There are various aspects to the package that need to be understood, to ensure an effective design. The focus of this paper is to understand the BGA reliability of the package with particular reference to comparison of the surface finish, vis-a`-vis, between Electroless Nickel Immersion Gold (ENIG) and Solder On Pad (SOP) on the substrate side of the package, which are the typical solutions for large plastic FC-BGA packages. Tests, which include board level temperature cycling, monotonic bend and shock testing have been conducted to compare the two surface finish options. The results of these tests demonstrate that the mechanical strength of the interface exceeds by a factor of two for the SOP surface finish, while BGA design parameters play a key role in ensuring comparative temperature cycle reliability in comparison with ENIG packages.

Solder-Joint Reliability of BGA Packages in Automotive Applications

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000236-000257 ◽  
Author(s):  
Burton Carpenter ◽  
Andrew Mawer ◽  
Mollie Benson ◽  
John Arthur ◽  
Betty Young
Keyword(s):  
Solder Joint ◽  
Flip Chip ◽  
Performance Test ◽  
Stress Test ◽  
Circuit Board ◽  
Cycle Performance ◽  
Temperature Cycle ◽  
Automotive Applications ◽  
Bga Packages ◽  
Board Level

The solder-joint interconnect between an IC component and the PCB (printed circuit board) is a critical link in the system overall reliability. Trends in the automotive market are driving increased focus on solder-joint performance: (1) increasing electronics content for new functions, especially for ADAS (advanced driver-assistance systems), (2) use in safety critical systems and sub-systems, (3) decreasing interconnect pitches which reduces the stand-off and available solder, (4) increasing industry reliability expectations, and (5) package variations (ex. multi-die). In particular, BGA (Ball Grid Array) packages are used throughout the vehicle across various systems including engine control, braking, communication, infotainment, and radar to name only a few. Among these, under-the-hood applications often require high sustained operating temperatures and many heating/cooling cycles during the vehicle lifetime. The reliability of these interconnects is routinely assessed by cyclical thermal stress (temperate cycling) of components mounted to boards. While AEC (Automotive Electronics Council) offers no standards for solder-joint testing (for example, board level reliability criteria is not included in the AEC Q100 “Failure Mechanism Based Stress Test Qualification for Integrated Circuits”), IPC 9701A “Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments” can be followed. For automotive under-the-hood the specified cycle range is 40°C to 125°C (TC3). This paper summarizes the BL-TC (board level temperature cycle) performance of various BGA packages used in automotive applications. In all cases the test vehicle packages were daisy-chain versions of production devices, while maintaining critical features such as BGA footprint, physical dimensions, BOM (bill of materials), die size and thickness and substrate layer metal densities. All used Pb-free solders for both the BGA solder ball and the paste printed onto the PCB. The PCB designs were complementary to the packages establishing daisy-chain connections winding through the PCB, the solder-joint and package substrate. Each chain (net) was continuously monitored in situ during cycling. An event detector logged a failure when a net resistance exceeded 300 ohms. Wirebonded and flip chip packages were studied, ranging in size from 10mm to 29mm with BGA pitches including 0.65mm, 0.80mm and 1.00mm. In addition to these primary attributes, various other factors were found to alter the solder-joint lifetimes. For example, increasing BGA pad and solder sphere diameters improved solder-joint lifetime, but increasing the PCB pad diameter often did not. Among solder materials, eutectic SnAg typically showed longer lifetimes than other high Ag SAC alloys such as SAC305 and SAC405. The addition of Bi to the SAC alloy showed promise for further improvements. Other factors that were studied include die thickness, die size, and BGA pad finish. Both mechanical cross-section and dye penetrant analysis (dye-and-pry) were employed for failure analysis, enabling study of crack propagation and crack location within the solder-joint. Additionally, failure location (failing solder-joint) was identified for each as package corner, under the die edge, or package center in a predictable pattern depending on the package type. Examined in total, two opposing trends will force future innovation. Industry reliability requirements continue to drive expectations (i.e. cycles to failure) higher, while increasing package size and decreasing pitch will naturally reduce the solder-joint lifetimes. Solutions will be found in package design, package material and solder selections.

Lead Free Flip Chip Reliability for Various Package Types

2011 ◽  
Author(s):  
Nokibul Islam ◽  
Miguel Jimarez ◽  
Ahmer Syed ◽  
TaeKyeong Hwang ◽  
JaeYun Gim ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Heat Dissipation ◽  
Coefficient Of Thermal Expansion ◽  
High Reliability ◽  
Large Body ◽  
Temperature Cycle ◽  
Molding Compound ◽  
Board Level ◽  
Board Level Reliability

Flip Chip (FC) technology has now become the mainstream solution for high performance packages. From commercial gaming machines to high reliability servers, the FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out to make the flip chip more robust, smaller foot prints, and excellent performance. FC packages are fabricated typically in two main configurations. Bare die FC packages leave the non active side of the die exposed. This allows the customer to apply their preferred heat dissipation scheme during board level attach. Lidded FC packages use a metallic lid attached to the die. Bare die package can be further subdivided into bare die underfilled package and bare die flip chip molded ball grid array (FCmBGA) package. Each of these packaging configurations has advantages as well as disadvantages. FCmBGA uses molding compound or EMC instead of capillary underfill, to protect FC die, and eliminate the need for a lid. Package warpage reduced a lot by adding a lid with the bare die FC package. However, the package and board level reliability for the above package types are still debatable. In this study test vehicles with three package types with bumps and BGAs are daisy chain to measure in situ data during accelerated tests. Impact of standard vs. low CTE (coefficient of thermal expansion) core substrate, accelerated temperature cycle conditions (temperature cycle condition “B”, “H”, and “J” according to JEDEC), and package level vs. package mounted on the board level reliability will be investigated. Comprehensive reliability data will help to select the right package type for next generation large die large body flip chip application.

A STUDY OF SURFACE FINISHES FOR IC SUBSTRATES AND WIRE BOND APPLICATIONS

2011 ◽  
Vol 2011 (1) ◽  
pp. 000516-000520 ◽  
Author(s):  
John Ganjei ◽  
Ernest Long ◽  
Lenora Toscano
Keyword(s):  
Surface Finish ◽  
Printed Circuit Boards ◽  
Performance Enhancement ◽  
High Reliability ◽  
Cost Effective ◽  
Electroless Nickel ◽  
Gold Wire ◽  
Electronics Industry ◽  
Surface Finishes ◽  
And Performance

The continuing drive for ever increasing performance enhancement in the electronics industry, in combination with the recent, very significant increase in precious metal costs have left fabricators and OEMs questioning what the best, most cost effective, surface finish is for high reliability applications. Currently, the IC substrate market relies heavily on electrolytic nickel and gold as a solderable and superior wire bondable surface. The use of this finish has allowed manufacturers to avoid the reliability concerns However, this choice also results in significant design restraints being imposed. Many in the industry are now investigating the use of electroless nickel/electroless palladium/immersion gold (ENEPIG) to achieve both high reliability and performance, without the negative design restraints imparted by the use of electrolytic processes. However, over the last year alone, the industry has watched the price of gold increase by 50% and that of palladium double [1]. With this in mind, and considering the historic precedent set in the mid 1990’s when ENEPIG was also evaluated as a surface finish for printed circuit boards, when coincidentally, the cost of palladium also reached an all time high, it should be remembered that the electronics industry quickly moved to evaluate alternate, more cost sustainable, surface finishes. This paper details the use of lower cost, alternate surface finishes for IC substrate applications, with particular experimental focus on gold wire bonding capabilities and BGA solderability of the finishes described. The paper also discusses related process cycle advantages and the significantly reduced operating costs associated with these new finishes.

Examination of Solder Interconnects Formed on ENEPIG Finished Printed Wiring Boards Under Drop Loading Conditions

2013 ◽  
Author(s):  
Adam Pearl ◽  
Michael Osterman
Keyword(s):  
Failure Mode ◽  
Surface Finish ◽  
Electroless Nickel ◽  
Primary Role ◽  
Mechanical Shock ◽  
Printed Wiring Boards ◽  
Printed Wiring Board ◽  
Bga Packages ◽  
Immersion Silver ◽  
Component Interface

Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), which has been used in component packaging, has been gaining attention as a surface finish for printed wiring boards. The primary role of a printed wiring board surface finish is to provide a solderable surface for assembly, creating a reliable solder interconnect. With regards to reliability, the increased use of mobile electronics has resulted in the need to consider the ability of interconnects to withstand repeated mechanical shocks. This paper examines the drop reliability of both SnPb and SAC305 interconnects formed on ENEPIG finished printed wiring boards. For comparison, the drop reliability test results for similar boards with Immersion Silver (ImAg) board finish are included. Test boards include BGA and resistor packages. The boards are dropped 500 times to achieve failure across the components. Failure analysis revealed that the dominant failure mode for BGA packages on the ENEPIG finish was cracking in the solder balls at the component interface, while for the ImAg finish the dominant failure mode was cratering in the board laminate below the solder pad. For the resistor packages, cracking through the solder joint at the component interface was the dominant failure mode for both the ENEPIG and ImAg finishes. The drop results indicate that both finishes are suitable for systems that could experience mechanical shock due to drop, with components soldered onto ENEPIG with a SAC 305 solder having the highest survivability. The combination of SnPb and ImAg was found to be superior to SAC 305 and ImAg.

Two-Layer Solder Resist Film with Low Young’s Modulus for High Reliability

2020 ◽  
Vol 2020 (1) ◽  
pp. 000307-000312
Author(s):  
YingHsuan Chou ◽  
Daichi Okamoto ◽  
Hidekazu Miyabe
Keyword(s):  
Thermal Resistance ◽  
Crack Resistance ◽  
Young’S Modulus ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Young's Modulus ◽  
Layer Structure ◽  
High Reliability ◽  
Bga Packages ◽  
Link Density

Abstract In this paper, we reveal the development of a novel two-layer Solder Resist (SR) film with low young’s modulus which consists of low young’s modulus layer that possesses excellent adhesion to substrate and thermal resistance layer which is composed of resins with high thermal resistance and great toughness. This novel two-layer SR film exhibits superior resolution and crack resistance. Furthermore, the amount of warpage is extremely low. In general, the material with low young’s modulus and high elongation is caused from weak cross-link density, resulting in poor thermal resistance and delamination which occurs when mounting at high temperature. Herein, we can inhibit delamination successfully by this new two-layer structure film with superior thermal resistance. The Coefficient of Thermal Expansion (CTE) of conventional SR for FC-BGA is 35 ppm, and modulus is 4.5 GPa, whereas, this advanced two-layer SR film exhibits CTE of 66 ppm, and modulus of 2.3 GPa. In order to compare the crack resistance between conventional SR and newly developed two-layer SR film, the film was laminated on BGA substrate (substrate size is 50 mm × 50 mm), patterned by photolithography and cured, and then, 25 mm × 25 mm chip was mounted on a BGA substrate by flip-chip bonder. Conducting thermal cycle test (TCT) and observing the number of cracks after 1000 cycles of TCT. The crack occurrence frequency of the conventional SR is 65 %, whereas that of the new two-layer SR film is 4 %. We proved clearly that high CTE and low young’s modulus demonstrate overwhelmingly high crack resistance. Besides, high resolution of this newly developed two-layer film enabled the formation of SR opening (SRO) as small as 40 μm. From the above results, the newly developed two-layer SR film with low young’s modulus is beneficial for the next generation high-density package, especially for the outermost layer of FC-BGA packages and interposers that require higher reliability.

High Reliability Underfill for Flip-Chip Application

1996 ◽  
Vol 445 ◽  
Author(s):  
K. Sumita ◽  
K. Kumagae ◽  
K. Dobashi ◽  
T. Shiobara ◽  
M. Kuroda
Keyword(s):  
Ring Opening ◽  
Flip Chip ◽  
High Reliability ◽  
Void Formation ◽  
Ring Opening Polymerization ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Excellent Adhesion ◽  
Reliability Performance ◽  
Modified Epoxy

AbstractA new underfill was developed for a flip chip application with a large VLSI die. The new underfill is resistant to hydrolysis, exhibits a significantly lower moisture saturation level than widely used carboxylic anhydride cured underfills, demonstrates superb penetration capability between such a large die and an organic substrate without void formation, and delivers excellent adhesion characteristics and reliability performance during temperature cycling test and PCT (pressure cooker test).The new underfill utilizes amine catalyzed ring opening polymerization of epoxides, forms ether linkages during cure rather than ester linkages which anhydride cured underfills form, and strongly resists to hydrolysis. The underfill is less sensitive to moisture contamination and provides improved floor life as well as storage life in contrast to anhydride cured underfills as well. Unique low stress performance and penetration capability of the underfill are attributed to the use of proprietary silicone modified epoxy resin as well as highly loaded filler of optimized size, shape and size distribution in reference to the gap between a die and an organic substrate.An optimum cure schedule and a desirable viscosity range have also been identified for the new underfill to minimize filler segregation. Proper preheating of a die‐substrate has effectively reduced void formation while facilitating the removal of volatile from an organic substrate.

Reliability of Anisotropically Conductive Adhesive Joints on a Flip-Chip/FR-4 Substrate

2002 ◽  
Vol 124 (3) ◽  
pp. 240-245 ◽  
Author(s):  
Johan Liu ◽  
Zonghe Lai
Keyword(s):  
Flip Chip ◽  
High Reliability ◽  
Low Cost ◽  
Adhesive Joints ◽  
Temperature Cycling ◽  
Conductive Adhesive ◽  
Resistance Measurement ◽  
Time To Failure ◽  
Low Cost Substrate

A reliability study on anisotropically conductive adhesive joints on a Flip-Chip/FR-4 assembly has been carried out. In the study, nine types of anisotropic conductive adhesive (ACA) and one nonconductive film (NCF) were used. In total, nearly one-thousand single joints were subjected to reliability tests in terms of temperature cycling between −40°C and 125°C with a dwell time of 15 minutes and a ramp rate of 110°C/min. The test chip used for this extensive reliability test had a pitch of 100 μm. Therefore, this work was particularly focused on evaluation on the reliability of ultra fine pitch flip-chip interconnections using anisotropically conductive adhesives on a low-cost substrate. The reliability was characterized by single contact resistance measurement using the four-probe method during temperature cycling testing up to 3000 cycles. The Mean Time To Failure (MTTF) (defined as 50% failure of all tested joints) are 650, 2500, and 3500 cycles when the failure definition is defined as 20% increase, larger than 50 mΩ and larger than 100 mΩ, respectively, using the in-situ electrical resistance measurement technique. Using the discontinuous (manual) measurement at room temperature by taking out the sample from the cycling chamber, the MTTF for the same joint system is around 2500 cycles in the case that the failure criteria is defined as 20% of the resistance increase, far better than the results from the in-situ measurement. The results show clearly that in optimized conditions, high reliability flip-chip anisotropically conductive adhesive joints on low-cost substrate can be achieved.

Effect of Soldier Bump Size On Interfacial Reactions During Soldering Between PB–Free Solder and Cu and Cu Ni/Pd/Au Surface Finishes

2012 ◽  
Author(s):  
Nor Akmal Fadil ◽  
Ali Ourdjini ◽  
Azmah Hanim Mohamed Ariff ◽  
Siti Rabiatul Aisha Idris
Keyword(s):  
Intermetallic Compounds ◽  
Surface Finish ◽  
Isothermal Aging ◽  
Flip Chip ◽  
Electroless Nickel ◽  
Lead Free ◽  
Lead Free Solder ◽  
Under Bump Metallization ◽  
Surface Finishes ◽  
Free Solder

Teknologi flip chip memberikan ketumpatan I/O yang sangat tinggi dan mengambil kira prestasi elektrikal yang paling baik dalam penyambungan komponen elektronik. Oleh itu, kajian tentang sebatian antara logam dilaksanakan untuk mengkaji kesan saiz bebola pateri bagi beberapa penyudahan permukaan, iaitu Kuprum dan Nikel tanpa elektrod/Palladium tanpa elektrod/Emas rendaman (ENEPIG). Pelogaman di bawah pateri (UBM) Ni/Pd/Au bagi aplikasi flip chip digunakan dengan sangat meluas dalam pembungkusan elektronik. Analisis FESEM dilakukan untuk menganalisis morfologi dan komposisi bagi sebatian antara logam (IMC). IMC yang terbentuk antara pateri Sn–Pb dan tanpa Pb dengan penyudahan permukaan kuprum semasa proses pematrian logam secara umumnya adalah (Cu, Ni)6Sn5 dan Cu6Sn5 dan Cu6Sn5. Sementara IMC utama yang terbentuk antara pateri Sn–Pb dan tanpa Pb dengan penyudahan permukaan ENEPIG adalah (Ni, Cu)3Sn4 dan Ni3Sn4. Hasil daripada analisis morfologi menggunakan FESEM dengan EDX menyatakan penuaan sesuhu pada suhu 150°C menyebabkan penebalan dan pengasaran struktur IMC serta menjadikan bentuknya kepada lebih sfera. Tebal IMC bagi kedua–dua penyudahan yang dikaji adalah lebih tinggi bagi bebola patri yang lebih kecil. Daripada hasil kajian juga, didapati bahawa kadar pertumbuhan IMC adalah lebih tinggi apabila pematrian dilakukan atas penyudahan kuprum berbanding ENEPIG. Hasil kajian juga menunjukkan ketebalan IMC adalah berkadaran dengan masa penuaan sesuhu. Kata kunci: Flip chip; Kumprum dan Nikel tanpa elektrod; Palladium tanpa elektrod; Emas rendaman (ENEPIG); Pelogaman di bawah pateri (UMB) Ni/Pd/Au Flip chip technology provides the ultimate in high I/O–density and count with superior electrical performance for interconnecting electronic components. Therefore, the study of the intermetallic compounds was conducted to investigate the effect of solder bumps sizes on several surface finishes which are copper and Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) which is widely used in electronics packaging as under–bump metallization (UBM) for flip–chip application nowadays. In this research, field emission scanning electron microscopy (FE–SEM) analyses were conducted to analyze the morphology and composition of intermetallic compounds (IMCs) formed at the interface between the solder and UBM. The IMCs between Sn–Pb and lead–free solder with Cu surface finish during reflowing were mainly (Cu, Ni)6Sn5 dan Cu6Sn5. While the main IMCs formed between Sn–Pb and lead–free solder on ENEPIG surface finish are (Ni, Cu)3Sn4 and Ni3Sn4. The results from FESEM with energy dispersive x–ray (EDX) have revealed that isothermal aging at 150°C has caused the thickening and coarsening of IMCs as well as changing them into more spherical shape. The thickness of the intermetallic compounds in both finishes investigated ware found to be higher in solders with smaller bump size. From the experimental results, it also appears that the growth rate of IMCs is higher when soldering on copper compared to ENEPIG finish. Besides that, the results also showed that the thickness of intermetallic compounds was found to be proportional to isothermal aging duration. Key words: Electroless nickel; electroless palladium; immersion gold (ENEPIG); flip chip; Ni/Pd/Au Under–bump metallization (UMB)

Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package

2013 ◽  
Vol 2013 (1) ◽  
pp. 000239-000244
Author(s):  
Michael Lyakas ◽  
Corey Reichman ◽  
Miguel Jimarez ◽  
Romina Mimi Ocampo ◽  
Aaron Elberg ◽  
...  
Keyword(s):  
High Power ◽  
Flip Chip ◽  
Mechanical Damage ◽  
Temperature Cycling ◽  
Technology Selection ◽  
Design Rule ◽  
Resistance Testing ◽  
Temperature Cycle ◽  
Reliability Testing ◽  
Component Level

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.

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