A low-power 802.11 ad compatible 60-GHz phase-locked loop in 65-nm CMOS

2015 ◽  
Vol 57 (3) ◽  
pp. 660-667
Author(s):  
Hammad M. Cheema ◽  
Muhammad Arsalan ◽  
Khaled N. Salama ◽  
Atif Shamim
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
60 Ghz

A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS

2009 ◽  
Vol E92-C (6) ◽  
pp. 785-791 ◽  
Author(s):  
Hiroaki HOSHINO ◽  
Ryoichi TACHIBANA ◽  
Toshiya MITOMO ◽  
Naoko ONO ◽  
Yoshiaki YOSHIHARA ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
60 Ghz

Fully integrated 60 GHz transceiver in SiGe BiCMOS, RF modules, and 3.6 Gbit/s OFDM data transmission

2011 ◽  
Vol 3 (2) ◽  
pp. 139-145 ◽  
Author(s):  
Srdjan Glisic ◽  
J. Christoph Scheytt ◽  
Yaoming Sun ◽  
Frank Herzel ◽  
Ruoyu Wang ◽  
...  
Keyword(s):  
Data Transmission ◽  
Intermediate Frequency ◽  
Phase Locked Loop ◽  
Data Rate ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Integrated ◽  
Front End ◽  
Free Data ◽  
Bicmos Technology

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Review on 60GHz Low Noise Amplifier for Low Power and Linearity

2017 ◽  
pp. 283-315
Author(s):  
Siva Sankar Yellampalli ◽  
Rashmi S. B.
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Radio Spectrum ◽  
Low Noise ◽  
Bias Current ◽  
60 Ghz ◽  
Current Reuse ◽  
Extremely High Frequency ◽  
Noise Amplifier ◽  
Circuit Components

In the extremely high frequency radio spectrum of 30-300 GHz, the band from 57-64 GHz has been de-regulated. The biggest challenge in designing products at this frequency is the design of CMOS based transceiver circuit components. This chapter deals with the review of 60 GHz LNA design. LNA was chosen as this is the first component of the receiver circuit and its performance affects the transceiver efficiency. In this chapter the review is done on 60GHz LNA's design addressing the linearization, and low power challenges. To address these challenges, in literature there are many LNA architectures such as simple cascode topology, Current reuse topology etc. The major advantage of current reuse topology is its load transistor shares the same bias current of driver which results in reduced power dissipation by maintaining the maximum gain. The main objective of this chapter is to address gain, power dissipation and linearization challenges by reviewing the different current reuse architectures and linearization techniques used to implement 60GHz LNA.

Highly-Integrated Low-Power 60 GHz Multichannel Transceiver for Radar Applications in 28 nm CMOS

2019 ◽  
Author(s):  
V. Issakov ◽  
R. Ciocoveanu ◽  
R. Weigel ◽  
A. Geiselbrechtinger ◽  
J. Rimmelspacher
Keyword(s):  
Low Power ◽  
60 Ghz ◽  
Radar Applications ◽  
28 Nm
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