P-1.1: Anomalous Dependence of Threshold Voltage on Channel Width and Drain Voltage in Back-channel-etched a-IGZO TFTs

3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.

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Impact of Device Structure on Neutron-Induced Single-Event Effect in SiC MOSFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.963.738 ◽

2019 ◽

Vol 963 ◽

pp. 738-741

Author(s):

Hiroshi Kono ◽

Teruyuki Ohashi ◽

Takao Noda ◽

Kenya Sano

Keyword(s):

Threshold Voltage ◽

Drift Region ◽

Single Event ◽

Drain Voltage ◽

Device Structure ◽

Pin Diodes ◽

Power Mosfets ◽

Single Event Effect ◽

Significant Difference ◽

Avalanche Breakdown Voltage

Neutron single event effect (SEE) tolerance of SiC power MOSFETs with different drift region design were evaluated. The SEE is detected over the SEE threshold voltage (VSEE). The failure rate increases exponentially as the drain voltage increases above VSEE. The device with higher avalanche breakdown voltage has higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes of the same epitaxial structure were also evaluated. There was no significant difference in the neutron SEE tolerance of these devices.

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Fabricaton Ofactive Devices and Logic Gates on Fibers

MRS Proceedings ◽

10.1557/proc-769-h8.6 ◽

2003 ◽

Vol 769 ◽

Author(s):

YongWoo Choi ◽

Ioannis Kymissis ◽

Annie Wang ◽

Akintunde I. Akinwande

Keyword(s):

Threshold Voltage ◽

Electronic Structures ◽

Low Cost ◽

Logic Gates ◽

Wearable Electronics ◽

Drain Voltage ◽

Large Area ◽

Active Devices ◽

P Type ◽

A Current

AbstractTextiles are a suitable substrate for large area, flexible and wearable electronics because of their excellent flexibility, mechanical properties and low cost manufacturability. The ability to fabricate active devices on fiber is a key step for achieving large area and flexible electronic structures. We fabricated transistors and inverters with a-Si film and pentacene film on Kapton film and cut them into fibers. The a-Si TFT showed a threshold voltage of 8.5 V and on/off ratio of 103 at a drain voltage of 10 V. These are similar to the characteristics of a TFT fabricated on a glass substrate at the same time. The maximum gain of the inverter with an enhancement n-type load was 6.45 at a drain voltage of 10 V. The pentacene OTFT showed a threshold voltage of -8 V and on/off ratio of 103 at a drain voltage of -30 V. The inverter with a depletion p-type load showed a voltage inversion but the inversion occurred at the wrong voltage. The antifuse was successfully programmed with a voltage pulse and also a current pulse. The resistance decreased from 10 GΩ to 2 kΩ after the programming.

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Design and Gate Drive Considerations for Epitaxial 1.2 kV Buried Grid N-on and N-off JFETs for Operation at 250°C

Materials Science Forum ◽

10.4028/www.scientific.net/msf.645-648.961 ◽

2010 ◽

Vol 645-648 ◽

pp. 961-964 ◽

Cited By ~ 3

Author(s):

Jang Kwon Lim ◽

Mietek Bakowski ◽

Hans Peter Nee

Keyword(s):

Threshold Voltage ◽

Doping Concentration ◽

Channel Length ◽

Channel Width ◽

Temperature Range ◽

Turn On ◽

Switching Losses ◽

Order Of Magnitude ◽

Gate Resistance

The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1 . For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch 0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.

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