Influence of drain voltage on MOSFET threshold voltage determination by transconductance change and gm/Id methods

2011 ◽  
Author(s):  
T. Rudenko ◽  
V. Kilchytska ◽  
M. K. Md Arshad ◽  
J.-P. Raskin ◽  
A. Nazarov ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Voltage

3 kV Normally-Off 4H-SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

2014 ◽  
Vol 778-780 ◽  
pp. 899-902 ◽  
Author(s):  
Akio Takatsuka ◽  
Yasunori Tanaka ◽  
Koji Yano ◽  
Norio Matsumoto ◽  
Tsutomu Yatsuo ◽  
...  
Keyword(s):  
Leakage Current ◽  
Leakage Current Density ◽  
Current Density ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Fabrication Process ◽  
Drain Voltage ◽  
Static Induction Transistors ◽  
Static Induction

3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.

Impact of Device Structure on Neutron-Induced Single-Event Effect in SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 738-741
Author(s):  
Hiroshi Kono ◽  
Teruyuki Ohashi ◽  
Takao Noda ◽  
Kenya Sano
Keyword(s):  
Threshold Voltage ◽  
Drift Region ◽  
Single Event ◽  
Drain Voltage ◽  
Device Structure ◽  
Pin Diodes ◽  
Power Mosfets ◽  
Single Event Effect ◽  
Significant Difference ◽  
Avalanche Breakdown Voltage

Neutron single event effect (SEE) tolerance of SiC power MOSFETs with different drift region design were evaluated. The SEE is detected over the SEE threshold voltage (VSEE). The failure rate increases exponentially as the drain voltage increases above VSEE. The device with higher avalanche breakdown voltage has higher SEE threshold voltage. The neutron SEE tolerance of MOSFETs and PiN diodes of the same epitaxial structure were also evaluated. There was no significant difference in the neutron SEE tolerance of these devices.

Fabricaton Ofactive Devices and Logic Gates on Fibers

2003 ◽  
Vol 769 ◽  
Author(s):  
YongWoo Choi ◽  
Ioannis Kymissis ◽  
Annie Wang ◽  
Akintunde I. Akinwande
Keyword(s):  
Threshold Voltage ◽  
Electronic Structures ◽  
Low Cost ◽  
Logic Gates ◽  
Wearable Electronics ◽  
Drain Voltage ◽  
Large Area ◽  
Active Devices ◽  
P Type ◽  
A Current

AbstractTextiles are a suitable substrate for large area, flexible and wearable electronics because of their excellent flexibility, mechanical properties and low cost manufacturability. The ability to fabricate active devices on fiber is a key step for achieving large area and flexible electronic structures. We fabricated transistors and inverters with a-Si film and pentacene film on Kapton film and cut them into fibers. The a-Si TFT showed a threshold voltage of 8.5 V and on/off ratio of 103 at a drain voltage of 10 V. These are similar to the characteristics of a TFT fabricated on a glass substrate at the same time. The maximum gain of the inverter with an enhancement n-type load was 6.45 at a drain voltage of 10 V. The pentacene OTFT showed a threshold voltage of -8 V and on/off ratio of 103 at a drain voltage of -30 V. The inverter with a depletion p-type load showed a voltage inversion but the inversion occurred at the wrong voltage. The antifuse was successfully programmed with a voltage pulse and also a current pulse. The resistance decreased from 10 GΩ to 2 kΩ after the programming.

Effects of Gate Line Width Roughness on Threshold-Voltage Fluctuation Among Short-Channel Transistors at High Drain Voltage

2010 ◽  
Vol 31 (3) ◽  
pp. 240-242 ◽  
Author(s):  
H. Fukutome ◽  
E. Yoshida ◽  
K. Hosaka ◽  
M. Tajima ◽  
Y. Momiyama ◽  
...  
Keyword(s):  
Line Width ◽  
Threshold Voltage ◽  
Drain Voltage ◽  
Voltage Fluctuation ◽  
Short Channel

Drain-voltage effects on the threshold voltage of a small-geometry MOSFET

1983 ◽  
Vol 26 (9) ◽  
pp. 851-860 ◽  
Author(s):  
C.S. Chao ◽  
L.A. Akers ◽  
D.N. Pattanayak
Keyword(s):  
Threshold Voltage ◽  
Drain Voltage

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part II—Effect of Drain Voltage

2011 ◽  
Vol 58 (12) ◽  
pp. 4180-4188 ◽  
Author(s):  
Tamara Rudenko ◽  
Valeriya Kilchytska ◽  
Mohd Khairuddin Md Arshad ◽  
Jean-Pierre Raskin ◽  
Alexey Nazarov ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Voltage ◽  
Current Ratio ◽  
Ratio Change

Physical Simulation of Drain-Induced Barrier Lowering Effect in SiC MESFETs

2005 ◽  
Vol 483-485 ◽  
pp. 849-852 ◽  
Author(s):  
C.L. Zhu ◽  
E. Rusli ◽  
J. Almira ◽  
Chin Che Tin ◽  
S.F. Yoon ◽  
...  
Keyword(s):  
Diffusion Model ◽  
Threshold Voltage ◽  
Physical Simulation ◽  
Gate Length ◽  
Drain Voltage ◽  
Short Channel ◽  
Threshold Voltage Shift ◽  
Channel Thickness ◽  
Simulation Results ◽  
And Diffusion

The drain-induced barrier lowering (DIBL) effect in 4H-SiC MESFETs has been studied using the physical drift and diffusion model. Our simulation results showed that the high drain voltage typically applied in short-channel 4H-SiC MESFETs could substantially reduce the channel barrier and result in large threshold voltage shift. It is also found that the DIBL effect is more dependent on the ratio of the gate length to channel thickness (Lg/a), rather than the channel thickness itself. In order to minimize the DIBL effect, the ratio of Lg/a should be kept greater than 3 for practical 4H-SiC MESFETs.

On the Origin of Threshold Voltage Instability under Operating Conditions of 4H-SiC n-Channel MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 473-476 ◽  
Author(s):  
Gregor Pobegen ◽  
Julietta Weisse ◽  
Martin Hauck ◽  
Heiko B. Weber ◽  
Michael Krieger
Keyword(s):  
Threshold Voltage ◽  
Energy Barrier ◽  
Room Temperature ◽  
Operating Conditions ◽  
Electron Trapping ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitors ◽  
Voltage Instability ◽  
Order Of Magnitude

We report on the threshold voltage () instability under operating conditions after gate bias switches at constant drain voltage for n-MOSFETs fabricated on 4H silicon carbide (4H-SiC). This effect occurs at room temperature and close to the of the device. We show that the origin of the instability is electron trapping into SiO2 over an energy barrier of (0.3-0.4) eV. These traps show similarities to traps previously observed in 4H-SiC MOS capacitors and labelled near interface traps (NITs). Further, the density of the traps can be reduced by one order of magnitude through post-oxidation annealing in nitric oxide atmosphere.

High Temperature Characterisation of 4H-SiC VJFET

2007 ◽  
Vol 556-557 ◽  
pp. 799-802 ◽  
Author(s):  
Praneet Bhatnagar ◽  
Nicolas G. Wright ◽  
Alton B. Horsfall ◽  
Konstantin Vassilevski ◽  
C. Mark Johnson ◽  
...  
Keyword(s):  
High Temperature ◽  
Temperature Coefficient ◽  
High Temperatures ◽  
Current Density ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Drain Current ◽  
Drain Voltage ◽  
Average Temperature

4H-SiC depletion mode (normally-on) VJFETs were fabricated and characterised at temperatures up to 377 °C. The device current density at drain voltage of 50 V drops down from 54 A/cm2 at room temperature to around 42 A/cm2 at 377 °C which is a 20 % reduction in drain current density. This drop in drain currents is much lower than previously reported values of a 30 % drop in JFETs at high temperatures. The average temperature coefficient of the threshold voltage was found to be -1.36 mV/°C which is smaller than for most Si FETs. We have found that these devices have shown good I-V characteristics upto 377 °C along with being able to retain its characteristics on being retested at room temperature.

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