Meliponiculture for Pollination Support, Yield Enhancement and Poverty Eradication

2016 ◽  
pp. 267-272
Author(s):  
S. Devanesan ◽  
K. S. Premila ◽  
K. K. Shailaja
Keyword(s):  
Yield Enhancement ◽  
Poverty Eradication

Ict “Tools” for Poverty Eradication and Economic Growth in Nigeria

2012 ◽  
Vol 2 (1) ◽  
pp. 013-019 ◽  
Author(s):  
N. A. Yekini ◽  
◽  
M.M. Rufai ◽  
B.T. Adetoba ◽  
A.K. Akinwole ◽  
...  
Keyword(s):  
Economic Growth ◽  
Poverty Eradication ◽  
Ict Tools

Zakat as a Measure of Social Justice in Islamic Finance : An Accountant’s Overview

2013 ◽  
Vol 1 (1) ◽  
pp. 64 ◽  
Author(s):  
Pranam Dhar
Keyword(s):  
Social Justice ◽  
Islamic Finance ◽  
Poverty Eradication ◽  
The Third ◽  
The Family ◽  
Additional Amount ◽  
Important Form

Zakat is an important form of religiously mandated charity under Islam. It is the third pillar of Islam. The giving of Zakat is important for Muslims, as this leads to purification of their wealth from all sins. This paper examines the role of Zakat as an instrument of social justice and poverty eradication in society. Each Muslim calculates his or her own Zakat individually. Generally, this involves the payment each year of two and a half percent of one's capital, after the needs of the family have been met. One can donate additional amount as an act of voluntary charity but Zakat is fundamental to every Muslim. Zakat is the Islamic contribution to social justice: those who have to give charity share the benefit of their prosperity to those who have fallen short. This is the Islamic approach to remove greed and envy and to purify one's soul based on good intentions. This is the institution of Zakat in Islam. The institution of Zakat serves to eradicate poverty in the community and uphold the light of Islam. Allah says “whatever is paid as Zakat for the sake of Allah shall be rewarded in manifolds”.

Population growth is a big speed breaker at this juncture in India

2019 ◽  
Vol 118 (9) ◽  
pp. 245-257
Author(s):  
Dr. DR Agarwal ◽  
Ms. Bhawna
Keyword(s):  
Population Growth ◽  
Continuous Process ◽  
Future Generation ◽  
World Population ◽  
Law And Order ◽  
Solid Waste Disposal ◽  
Poverty Eradication ◽  
Conservation Of Natural Resources ◽  
Desired Family Size ◽  
Acute Crisis

After the dawn of independence in 1947, India moved on the path of planned development after launching a series of five years plans with the objective of creating a socialistic pattern of society that is the growth with social justice. In a welfare society, the functions of the govt. increases extensively and intensively. Gone are the days when functions of the govt. were limited to internal law and order and war preparedness (internal and external security). To provide all basic needs of the lowest and disadvantageous section of the society is considered to be duty of the govt. Education, health, power, sanitation, transport, communication, growth through distributive justice, linking of employment process with planned development, balanced regional development, social welfare and social security, clean drinking water, rural development, expansion of production and productive resources, equitable distribution of income and assets, removal of poverty, eradication of illiteracy, reduction in regional disparities, price stability, empowerment of the weaker section of the society, research and development with application of science, improvement in technology and productivity, conservation of natural resources for future generation, continuous process of change for better standard of life, human dignity and values, environmental balances etc. On the other side, India’s population grew at 1.2% a year between 2010 and 2019 marginally higher than global average of 1.1% a year in this period, but more than double china’s 0.5% a year according to UN population fund state of the world’s population 2018, released on 10-04-2019. India’s population growth = Population growth rate of China + Population growth of US = 0.5 + 0.7. Moreover, actual fertility rate children per women is 2.1 against the desired family size of 1.8. India has over 18% of the world population but just 4% of its fresh water resources. This is going to create a big demand for all kinds of commodities. The propensity to generate waste is increasing (waste is associated with food such as milk packets and water bottles piling up and solid waste disposal is acute crisis in big cities). All efforts of growth of G D P may go futile, if population growth remains unchecked. This paper highlights the consequences.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

Transmission Electron Microscopy and Scanning Capacitance Microscopy Analysis of Dislocation-Induced Leakages in n-channel I/O Transistors

2005 ◽  
Author(s):  
M.L. Anderson ◽  
P. Tangyunyong ◽  
T.A. Hill ◽  
C.Y. Nakakura ◽  
T.J. Headley ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
New Product Development ◽  
Yield Enhancement ◽  
Product Development Process ◽  
Product Lines ◽  
Scanning Capacitance Microscopy ◽  
Transmission Electron ◽  
Complementary Techniques ◽  
Analytical Tools

Abstract By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

Case Study in Fault Isolation of a Metal Short for Yield Enhancement

2010 ◽  
Author(s):  
Sarven Ipek ◽  
David Grosjean
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Photon Emission ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Analysis Technique ◽  
Laser Signal ◽  
Signal Injection ◽  
Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

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