Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

2014 ◽  
Vol 13 (2) ◽  
pp. 467-476 ◽  
Author(s):  
Gopi Krishna Saramekala ◽  
Abirmoya Santra ◽  
Mirgender Kumar ◽  
Sarvesh Dubey ◽  
Satyabrata Jit ◽  
...  
Keyword(s):  
Subthreshold Swing ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Subthreshold Current ◽  
Dual Metal

scholarly journals In1-xGaxAs Double Metal Gate-Stacking Cylindrical Nanowire MOSFET for highly sensitive Photo detector

2021 ◽  
Author(s):  
Sanjeev Kumar Sharma ◽  
Parveen Kumar ◽  
Balwant Raj ◽  
Balwinder Raj
Keyword(s):  
Fast Response ◽  
Short Channel Effects ◽  
Metal Gate ◽  
Short Channel ◽  
Subthreshold Current ◽  
Highly Sensitive ◽  
Channel Effects ◽  
Dual Metal ◽  
Silvaco Atlas ◽  
Nanowire Mosfet

Abstract This paper proposed a highly sensitive Double Metal Gate-stacking Cylindrical Nanowire-MOSFET (DMG CL-NWMOSFET) photosensor by using In1 − xGaxAs. For the best control of short channel effects (SCEs), a double metal gate has been utilized and for efficient photonic absorption, III-V compound has been utilized as channel material. The currently available Conventional Filed-Effect-Transistors (CFET) based photosensor have been used threshold voltage as parameter for the calculation of sensitivity, but in the proposed photosensor, change in subthreshold current has been used as the detecting parameters for sensitivity (Iillumination/Idark). The scientifically electrons study and the photo-conductive characteristics of In1 − xGaxAs CL-NWMOSFET are taken through Silvaco Atlas Tools. After the analysis of In1 − xGaxAs dual Metal Gate Stacking Cylindrical NWMOSFET responds to detectable spectrum (~ 450 nm), incidents light with constant, reversible and fast response by responsivity (4.3 mAW− 1), high Iillumination/Idark (1.36 * 109) and quantum-efficiency (1.12 %). The obtained results of In1 − xGaxAs DMG CL-NWMOSFET based photodetectors have the potential in optoelectronics applications.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

2009 ◽  
Vol 53 (3) ◽  
pp. 256-265 ◽  
Author(s):  
Rathnamala Rao ◽  
Guruprasad Katti ◽  
Dnyanesh S. Havaldar ◽  
Nandita DasGupta ◽  
Amitava DasGupta
Keyword(s):  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Metal Gate ◽  
Fully Depleted ◽  
Dual Metal ◽  
Threshold Voltage Model

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

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