Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Design and analysis of SHE-assisted STT MTJ/CMOS logic gates

2021 ◽  
Author(s):  
Prashanth Barla ◽  
Vinod Kumar Joshi ◽  
Somashekara Bhat
Keyword(s):  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Orbit Interaction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Oxide Semiconductor ◽  
Metal Materials ◽  
Power Delay Product

AbstractWe have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.

A new approach to bypass wire crossing problem in QCA nano technology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy
Keyword(s):  
Power Dissipation ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Nano Technology ◽  
New Approach ◽  
Content Type ◽  
Wire Crossing

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

A novel design of nano router with high-speed crossbar scheduler for digital systems in QCA paradigm

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Kalpana Kasilingam ◽  
Paulchamy Balaiah
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Modern Technology ◽  
Oxide Semiconductor ◽  
Large Area ◽  
Content Type ◽  
Compact Size ◽  
High Power Consumption ◽  
High Speed Data

Purpose The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power. Design/methodology/approach In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size. Findings This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area. Research limitations/implications To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler. Practical implications The simulation of the planned circuit with notional information established the practical identity of the scheme. Social implications The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. Originality/value The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.

CNTFET-Based Memory Design

2020 ◽  
pp. 16-36
Author(s):  
Shashi Bala ◽  
Mamta Khosla ◽  
Raj Kumar
Keyword(s):  
Random Access ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Suitable Alternative ◽  
Memory Design ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Power ◽  
Effect Transistor

As the feature size of device has been scaling down for many decades, conventional CMOS technology-based static random access memory (SRAM) has reached its limit due to significant leakage power. Therefore, carbon nanotube field effect transistor (CNTFET) can be considered most suitable alternative for SRAM. In this chapter, the performance and stability of CNTFET-based SRAM cells have been analyzed. Numerous figures of merit (FOM) (e.g., read/write noise margin, power dissipation, and read/write delay) have been considered to analyze the performance of CNTFET-based. The static power consumption in CNTFET-based SRAM cell was compared with conventional complementary metal oxide semiconductor (CMOS)-based SRAM cell. Conventional CNTFET and tunnel CNTFET-based SRAMs have also been considered for comparison. From the simulation results, it is observed that tunnel CNTFET SRAM cells have shown improved FOM over conventional CNTFET 6T SRAM cells without losing stability.

STDP implementation using multi-state spin-orbit torque synapse

2021 ◽  
Author(s):  
Hamdam Ghanatian ◽  
Margherita Ronchini ◽  
Hooman Farkhani ◽  
Farshad Moradi
Keyword(s):  
Learning Algorithm ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Spike Timing ◽  
Oxide Semiconductor ◽  
Spin Orbit ◽  
Ultra Low Power ◽  
Artificial Neural Network Ann ◽  
State Spin

Abstract The abundance of data to be processed calls for new computing paradigms, which could accommodate, and directly map artificial neural network (ANN) architectures at the hardware level. Neuromorphic computing has emerged as a potential solution, proposing the implementation of artificial neurons and synapses on physical substrates. Conventionally, neuromorphic platforms are deployed in complementary metal-oxide–semiconductor (CMOS) technology. However, such implementations still cannot compete with the highly energy-efficient performance of the brain. This calls for novel ultra-low-power nano-scale devices with the possibility of upscaling for the implementation of complex networks. In this paper, a multi-state spin-orbit torque (SOT) synapse based on the three-terminal perpendicular-anisotropy magnetic tunnel junction (P-MTJ) is proposed. In this implementation, P-MTJs use common heavy metals (HMs) but with different cross-section areas, thereby creating multiple states that can be harnessed to implement synapses. The proposed multi-state SOT synapse can solve the state-limited issue of spin-based synapses. Moreover, it is shown that the proposed multi-state SOT synapse can be programmed to reproduce the spike-timing-dependent plasticity (STDP) learning algorithm.

scholarly journals Inkjet-printed low-dimensional materials-based complementary electronic circuits on paper

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Irene Brunetti ◽  
Lorenzo Pimpolari ◽  
Silvia Conti ◽  
Robyn Worsley ◽  
Subimal Majee ◽  
...  
Keyword(s):  
Hexagonal Boron Nitride ◽  
Flexible Substrate ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Building Blocks ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wearable Electronics ◽  
Low Dimensional ◽  
Low Dimensional Materials

AbstractComplementary electronics has represented the corner stone of the digital era, and silicon technology has enabled this accomplishment. At the dawn of the flexible and wearable electronics age, the seek for new materials enabling the integration of complementary metal-oxide semiconductor (CMOS) technology on flexible substrates, finds in low-dimensional materials (either 1D or 2D) extraordinary candidates. Here, we show that the main building blocks for digital electronics can be obtained by exploiting 2D materials like molybdenum disulfide, hexagonal boron nitride and 1D materials such as carbon nanotubes through the inkjet-printing technique. In particular, we show that the proposed approach enables the fabrication of logic gates and a basic sequential network on a flexible substrate such as paper, with a performance already comparable with mainstream organic technology.

scholarly journals New efficient designs of reversible logic gates and circuits in the QCA technology

2019 ◽  
Vol 39 (1) ◽  
pp. 47-59 ◽  
Author(s):  
Abbas Rezaei
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Switching Speed ◽  
Parity Checker ◽  
Wire Crossing ◽  
Low Power Dissipation ◽  
Minimum Number ◽  
Reversible Logic Gates

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

Design and simulation of electro-thermal compliant MEMS logic gates

2018 ◽  
Vol 37 (2) ◽  
pp. 868-889 ◽  
Author(s):  
Pandiyan P. ◽  
Uma G. ◽  
Umapathy M.
Keyword(s):  
Logic Gate ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Micro Electro Mechanical System ◽  
Mechanical Analysis ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Out Of Plane ◽  
Compliant Actuator ◽  
The Given

PurposeThe purpose of this paper is to design an out-of-plane micro electro-thermal-compliant actuator based logic gates which work analogously to complementary metal oxide semiconductor (CMOS) based logic gates. The proposed logic gates used a single-bit mechanical micro ETC actuator per logic instead of using 6-14 individual transistors as in CMOS. Design/methodology/approachA complete analytical modelling is performed on a single ETC vertical actuator, and a relation between the applied voltage and the out-of-plane deflection is derived. Its coupled electro-thermo-mechanical analysis is carried out using micro electro mechanical system (MEMS) CAD tool CoventorWare to illustrate its performance. FindingsThis paper reports analytical and numerical simulation of basic MEMS ETC actuator-based logic gates. The proposed logic gate operates on 5 V, which suits well with conventional CMOS logic, which in turn reduces the power consumption of the device. Originality/valueThe proposed logic gates uses a single-bit MEMS ETC actuator per logic instead of using more transistors as in CMOS. The unique feature of this proposed logic gates is that the basic mechanical ETC actuator is customized in its structure to function as specific logic gates depending upon the given inputs.

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