Power consumption reduction in built-in self-test circuits

Journal of Ambient Intelligence and Humanized Computing ◽

10.1007/s12652-021-03363-x ◽

2021 ◽

Author(s):

Mohsen Askarzadeh ◽

Majid Haghparast ◽

Sam Jabbehdari

Keyword(s):

Power Consumption ◽

Consumption Reduction ◽

Self Test ◽

Built In Self Test

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A built-in self-test design with low power consumption based on genetic algorithm

2009 9th International Conference on Electronic Measurement & Instruments ◽

10.1109/icemi.2009.5274527 ◽

2009 ◽

Author(s):

Enmin Tan ◽

Li Wang

Keyword(s):

Genetic Algorithm ◽

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Test Design ◽

Self Test ◽

Built In Self Test

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The power consumption reducing technique of the pseudo-random test pattern generator and the signature analyzer for the built-in self-test

The Experience of Designing and Application of CAD Systems in Microelectronics, 2003. CADSM 2003. Proceedings of the 7th International Conference. ◽

10.1109/cadsm.2003.1255008 ◽

2004 ◽

Author(s):

I. Murashko ◽

V. Yarmolik ◽

M. Puczko

Keyword(s):

Power Consumption ◽

Test Pattern ◽

Pattern Generator ◽

Random Test ◽

Signature Analyzer ◽

Self Test ◽

Built In Self Test

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Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2014.0308083 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11487-11495

Author(s):

S. Nagaraju ◽

Ch.N.L. Sujatha ◽

J.S.S. Ramaraju

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Benchmark Circuit ◽

Self Test ◽

Built In Self Test

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The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

IEICE Transactions on Electronics ◽

10.1587/transele.e92.c.352 ◽

2009 ◽

Vol E92-C (3) ◽

pp. 352-355

Author(s):

Ki-Sang JUNG ◽

Kang-Jik KIM ◽

Young-Eun KIM ◽

Jin-Gyun CHUNG ◽

Ki-Hyun PYUN ◽

...

Keyword(s):

Power Consumption ◽

Compression Method ◽

Chip Area ◽

Consumption Reduction

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Memory Implementation in a System on Chip with Built-in Self-Test and Recovery Tools

Proceedings of Universities ELECTRONICS ◽

10.24151/1561-5405-2019-24-3-239-247 ◽

2019 ◽

Vol 24 (3) ◽

pp. 239-247

Author(s):

Vladimir G. Ryabtsev ◽

◽

Sergey V. Volobuev ◽

Keyword(s):

System On Chip ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

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RF Phase Error Built-In-Self-Test for A GSM SOC

i-manager’s Journal on Electrical Engineering ◽

10.26634/jee.1.4.378 ◽

2008 ◽

Vol 1 (4) ◽

pp. 39-44

Author(s):

Dallas Webster ◽

Loi Phan ◽

Oren Eliezer ◽

Rick Hudgens ◽

Donald Lie

Keyword(s):

Phase Error ◽

Self Test ◽

Built In Self Test

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Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3427911 ◽

2021 ◽

Vol 26 (3) ◽

pp. 1-18

Author(s):

Mehmet Ince ◽

Ender Yilmaz ◽

Wei Fu ◽

Joonsung Park ◽

Krishnaswamy Nagaraj ◽

...

Keyword(s):

Phase Locked Loops ◽

Test And Evaluation ◽

Self Test ◽

Built In Self Test

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IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270909 ◽

2004 ◽

Author(s):

J.J. Nejedlo

Keyword(s):

Next Generation ◽

Pci Express ◽

Self Test ◽

Built In Self Test ◽

Test Architecture ◽

Generation Test

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Built-in-self-test 3-D ring oscillator for stacked 3DIC

2014 IEEE International Symposium on Radio-Frequency Integration Technology ◽

10.1109/rfit.2014.6933251 ◽

2014 ◽

Author(s):

Cheng Jin ◽

Ni Wang ◽

Xiaowen Xu ◽

Houjun Sun

Keyword(s):

Ring Oscillator ◽

Self Test ◽

Built In Self Test

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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763109 ◽

2011 ◽

Author(s):

A Strano ◽

C Gómez ◽

D Ludovici ◽

M Favalli ◽

M E Gómez ◽

...

Keyword(s):

Network On Chip ◽

Structural Redundancy ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Test Architecture

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