The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction

2009 ◽  
Vol E92-C (3) ◽  
pp. 352-355
Author(s):  
Ki-Sang JUNG ◽  
Kang-Jik KIM ◽  
Young-Eun KIM ◽  
Jin-Gyun CHUNG ◽  
Ki-Hyun PYUN ◽  
...  
Keyword(s):  
Power Consumption ◽  
Compression Method ◽  
Chip Area ◽  
Consumption Reduction

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

scholarly journals Novel Superhydrophobic Surface with Solar-Absorptive Material for Improved De-Icing Performance

Materials ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 2758 ◽  
Author(s):  
Joseph Gonzales ◽  
Daiki Kurihara ◽  
Tetsuro Maeda ◽  
Masafumi Yamazaki ◽  
Takahito Saruhashi ◽  
...  
Keyword(s):  
Solar Radiation ◽  
Power Consumption ◽  
Superhydrophobic Surface ◽  
Radiation Absorption ◽  
Melting Time ◽  
Ice Accretion ◽  
Superhydrophobic Coating ◽  
Heating Source ◽  
Consumption Reduction ◽  
Ice Conditions

Ice accretion is detrimental to numerous industries, including infrastructure, power generation, and aviation applications. Currently, some of the leading de-icing technologies utilize a heating source coupled with a superhydrophobic surface. This superhydrophobic surface reduces the power consumption by the heating element. Further power consumption reduction in these systems can be achieved through an increase in passive heat generation through absorption of solar radiation. In this work, a superhydrophobic surface with increased solar radiation absorption is proposed and characterized. An existing icephobic surface based on a polytetrafluoroethylene (PTFE) microstructure was modified through the addition of graphite microparticles. The proposed surface maintains hydrophobic performance nearly identical to the original superhydrophobic coating as demonstrated by contact and roll-off angles within 2.5% of the original. The proposed graphite coating also has an absorptivity coefficient under exposure to solar radiation 35% greater than typical PTFE-based coatings. The proposed coating was subsequently tested in an icing wind tunnel, and showed an 8.5% and 50% decrease in melting time for rime and glaze ice conditions, respectively.

Power consumption reduction through elastic data rate adaptation in survivable multi-layer optical networks

2014 ◽  
Vol 28 (3) ◽  
pp. 276-286 ◽  
Author(s):  
Jordi Perelló ◽  
Annalisa Morea ◽  
Salvatore Spadaro ◽  
Albert Pagès ◽  
Sergio Ricciardi ◽  
...  
Keyword(s):  
Power Consumption ◽  
Optical Networks ◽  
Rate Adaptation ◽  
Data Rate ◽  
Consumption Reduction ◽  
Elastic Data

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

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