Structural morphological and electrical analysis of Pr- And La-doped magnesium ferrites

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

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Failure Analysis of Single Shared Column Fail in DRAM Using Nano-Probing Technique

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0423 ◽

2008 ◽

Author(s):

Suk Min Kim ◽

Jung Ho Lee ◽

Jong Hak Lee ◽

Hyung Ki Kim ◽

Myung Sick Chang ◽

...

Keyword(s):

Failure Analysis ◽

Failure Mechanisms ◽

Electrical Characteristics ◽

The Future ◽

Electrical Analysis

Abstract We report an analysis of a single shared column fail on DRAM technology using a nano-probing technique in this work. The electrical characteristics of the failed transistors show that the column fails were caused by two different failure mechanisms: abnormal contact and implant profiles. We believe that electrical analysis using nano-probing will be a powerful tool for non-visible failure analysis in the future because it is impossible to clearly reveal these two different failure mechanisms solely using physical failure methods.

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Quantitative Electrical Analysis of FIB Prepared Vias on BiCMOS and CMOS090 Designs

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0067 ◽

2006 ◽

Author(s):

B. Domengès ◽

P. Poirier

Keyword(s):

Ion Beam ◽

Beam Current ◽

Kelvin Probe ◽

Metal Line ◽

Cross Sectional ◽

Probe Technique ◽

Cross Sectional Analysis ◽

Controlling Parameter ◽

Electrical Analysis ◽

Sectional Analysis

Abstract In this study, the resistance of FIB prepared vias was characterized by the Kelvin probe technique and their physical characteristics studied using cross-sectional analysis. Two domains of resistivity were isolated in relation to the ion beam current used for the deposition of the via metal (Pt). Also submicrometer vias were investigated on 4.2 µm deep metal lines of a BiCMOS aluminum based design and a CMOS 090 copper based one. It is shown that the controlling parameter is the shape and volume of the contact, and that the contact formation is favored by the amount of over-mill of the via into the metal line it will contact.

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Non-Visible Defect Analysis of OTP Device

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0198 ◽

2011 ◽

Author(s):

C.Q. Chen ◽

G.B. Ang ◽

Z.X. Xing ◽

Y.N. Hua ◽

Z.Q. Mo ◽

...

Keyword(s):

Trap Center ◽

Data Retention ◽

Auger Analysis ◽

Cross Sectional ◽

Critical Dimensions ◽

Charge Trap ◽

Root Cause ◽

Transmission Electron ◽

Electrical Analysis ◽

Visible Defect

Abstract Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

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Identifying the Root Cause of Source-Drain Leakage Caused Soft Fail in Advanced Bulk FinFET Devices

10.31399/asm.cp.istfa2018p0383 ◽

2018 ◽

Author(s):

Liangshan Chen ◽

Yuting Wei ◽

Tanya Schaeffer ◽

Chongkhiam Oh

Keyword(s):

Careful Analysis ◽

Physical Analysis ◽

Device Structure ◽

Tem Analysis ◽

Root Cause ◽

3D Architecture ◽

Cause Of Failure ◽

Electrical Analysis ◽

Electrical Data

Abstract The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.

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