Identifying the Root Cause of Source-Drain Leakage Caused Soft Fail in Advanced Bulk FinFET Devices

2018 ◽  
Author(s):  
Liangshan Chen ◽  
Yuting Wei ◽  
Tanya Schaeffer ◽  
Chongkhiam Oh
Keyword(s):  
Careful Analysis ◽  
Physical Analysis ◽  
Device Structure ◽  
Tem Analysis ◽  
Root Cause ◽  
3D Architecture ◽  
Cause Of Failure ◽  
Electrical Analysis ◽  
Electrical Data

Abstract The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.

scholarly journals Identification of Yield Limiting Defects in a 0.5 Micron, Shallow Trench Isolation Technology

1999 ◽  
Author(s):  
Christopher L. Henderson ◽  
Charles E. Hembree ◽  
Jerry M. Soden ◽  
Thomas J. Headley ◽  
Bruce L. Draper
Keyword(s):  
Power Supply ◽  
Random Access ◽  
Shallow Trench Isolation ◽  
Root Cause ◽  
Trench Isolation ◽  
Static Random Access Memories ◽  
Cause Of Failure ◽  
Radiation Hardened ◽  
Supply Current ◽  
Electrical Analysis

Abstract During the development and qualification of a radiation-hardened, 0.5 μm shallow trench isolation technology, several yield-limiting defects were observed. The 256K (32K x 8) static-random access memories (SRAMs) used as a technology characterization vehicle had elevated power supply current during wafer probe testing. Many of the die sites were functional, but exhibited quiescent power supply current (IDDQ) in excess of 100 μA, the present limit for this particular SRAM. Initial electrical analysis indicated that many of the die sites exhibited unstable IDDQ that fluctuated rapidly. We refer to this condition as “jitter.” The IDDQ jitter appeared to be independent of temperature and predominately associated with the larger 256K SRAMs and not as prevalent in the 16K SRAMs (on the same reticle set). The root cause of failure was found to be two major processing problems: salicide bridging and stress-induced dislocations in the silicon island

Electrical Signature Verification of a Lightly Doped Drain Profile Abnormality in a 65nm Device via Nano-Probing and Junction Stain TEM

2009 ◽  
Author(s):  
Jie Su ◽  
Sanan Liang ◽  
Yoyo Wen ◽  
May Yang ◽  
Linfeng Wu ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Memory Function ◽  
Random Access ◽  
Signature Verification ◽  
Physical Analysis ◽  
Electronic Microscopy ◽  
Access Memory ◽  
Tem Analysis ◽  
Root Cause ◽  
Lightly Doped Drain

Abstract Failures caused by threshold voltage (Vt) shifts in sub-100nm technology transistors have become very difficult to both analyze and determine the failure mechanism. The failure mechanisms for Vt shifts are typically non-visible for traditional physical analysis methods such as SEM inspection or traditional TEM analysis. This paper demonstrates how nano-probing was used to carefully and fully characterize the Vt shift failure to determine a specific electrical signature for a specific failure mechanism and then with junction stain Transmission Electronic Microscopy (TEM) verify the subtle doping defect affecting the Static Random Access Memory function in the 65nm generation node. Device failure due to a lack of Lightly Dope Drain (LDD) implant induced by an inconspicuous spacer defect was determined to be the root cause of the failure.

scholarly journals Forensic Engineering Use Of The Safety Hierarchy

2005 ◽  
Vol 22 (1) ◽  
Author(s):  
John N. Schwartzberg
Keyword(s):  
Forensic Analysis ◽  
Case Histories ◽  
Analytical Technique ◽  
Root Cause ◽  
Hazard Control ◽  
Hazard Avoidance ◽  
Cause Of Failure ◽  
Forensic Engineering ◽  
Process Failures

The Safety Hierarchy Is A Recognized Linear Logical Approach To Hazard Control Most Commonly Utilized By Safety Professionals In Hazard Avoidance. In This Paper, Use Of This Method Of Analysis Is Introduced As A Method Of Forensic Analysis Of Product Failures, Workplace And Premises Liability Accidents, And Process Failures To Help Identify The Root Cause Of Failure And The Role Of The Responsible Entity In Causation. Examples And Case Histories Will Be Used To Demonstrate The Effectiveness Of The Analytical Technique.

Characterization of Gate Oxide Pinhole Defect in NMOS FinFET Devices

2017 ◽  
Author(s):  
Liangshan Chen ◽  
Arnaud Bousquet ◽  
Tanya Schaeffer ◽  
Lucile C. Teague Sheridan ◽  
Lowell Hodgkins ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Electron Tomography ◽  
Gate Oxide ◽  
The Other ◽  
Physical Analysis ◽  
Tem Analysis ◽  
Root Cause ◽  
The Common ◽  
Tomography Analysis

Abstract This paper highlights the application of nanoprobing technique and electron tomography analysis to characterize the tiny gate oxide pinhole defect in NMOS FinFET devices. Nanoprobing technique was utilized to achieve a better understanding on the failure mechanism by characterizing the device electrical behaviors, and electron tomography, capable of mitigating the common projection issue encountered by general TEM analysis, was applied for physical analysis. It has been demonstrated through two cases, one logic fail and the other memory fail, that these two techniques together can effectively identify the root cause of pinhole defect. This type of pinhole defect, characterized by a tiny spot of oxide discontinuity and without excessive materials inter-diffusion, has been extremely challenging in FA analysis. This paper will provide the analysis details leading to the successful characterization of such type of oxide pinhole defect.

Reliability Evaluation and Failure Analysis for NTC Thermistor

2003 ◽  
Vol 17 (08n09) ◽  
pp. 1254-1260 ◽  
Author(s):  
Joon Sik Jung ◽  
Jin Woo Kim ◽  
Myung Soo Kim ◽  
Joong Soon Jang ◽  
Dong Su Ryu
Keyword(s):  
Life Stress ◽  
Electrical Parameter ◽  
Accelerated Life Test ◽  
Physical Analysis ◽  
Root Cause ◽  
Accelerated Life ◽  
Field Samples ◽  
Ntc Thermistor ◽  
Cause Of Failure ◽  
Non Destructive

Failures of NTC thermistor are analyzed. Visual inspection, electrical parameter test, non-destructive test, and destructive physical analysis were performed on the field samples to identify the root cause of failure. It was found that the predominant failure mechanism was the copper migration of dumet (copper-clad alloy) at glass-PVC interface for glass-coated chip type NTC thermistor molded with PVC. Next, an accelerated life test is designed to predict the lifetime. Temperature, voltage, and humidity are considered as accelerating variables. Under the assumptions of a general life-stress relationship and Weibull lifetime distribution, the parameters of life-stress relationship and acceleration factor for the migration are estimated by analyzing the test data.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Marginal RF Gain Investigation and Root Cause Determination

2013 ◽  
Author(s):  
Keith Harber ◽  
Steve Brockett
Keyword(s):  
Radio Frequency ◽  
Failure Analysis ◽  
Power Amplifier ◽  
Physical Analysis ◽  
Root Cause ◽  
S Parameter ◽  
Mode Of Operation ◽  
S Parameters

Abstract This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.

Non-Visible Defect Analysis of OTP Device

2011 ◽  
Author(s):  
C.Q. Chen ◽  
G.B. Ang ◽  
Z.X. Xing ◽  
Y.N. Hua ◽  
Z.Q. Mo ◽  
...  
Keyword(s):  
Trap Center ◽  
Data Retention ◽  
Auger Analysis ◽  
Cross Sectional ◽  
Critical Dimensions ◽  
Charge Trap ◽  
Root Cause ◽  
Transmission Electron ◽  
Electrical Analysis ◽  
Visible Defect

Abstract Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

2000 ◽  
Author(s):  
J. N. C. de Luna ◽  
M. O. del Fierro ◽  
J. L. Muñoz
Keyword(s):  
Flash Memory ◽  
Electromagnetic Interference ◽  
Yield Loss ◽  
High Amplitude ◽  
Physical Analysis ◽  
Input Buffer ◽  
Automated Test Equipment ◽  
Root Cause ◽  
Root Cause Identification ◽  
Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

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