A new power supply strategy for high power rectifying units in electrolytic copper process

Author(s):  
He-Miao Liu ◽  
Yu-Lian Zhao ◽  
Yan-Ming Cheng ◽  
Jing Wu ◽  
Mahmoud A. M. Al Shurafa ◽  
...  
2005 ◽  
Vol 1 (03) ◽  
pp. 396-402
Author(s):  
A. Sudrià ◽  
◽  
E. Jaureguialzo ◽  
A. Samper ◽  
R. Villafáfila ◽  
...  

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  

2001 ◽  
Vol 37 (9) ◽  
pp. 597
Author(s):  
H.C. Chiu ◽  
S.C. Yang ◽  
F.T. Chien ◽  
Y.J. Chan

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1228
Author(s):  
Marcin Winnicki ◽  
Artur Wiatrowski ◽  
Michał Mazur

High Power Impulse Magnetron Sputtering (HiPIMS) was used for deposition of indium tin oxide (ITO) transparent thin films at low substrate temperature. A hybrid-type composite target was self-prepared by low-pressure cold spraying process. Prior to spraying In2O3 and oxidized Sn powders were mixed in a volume ratio of 3:1. Composite In2O3/Sn coating had a mean thickness of 900 µm. HiPIMS process was performed in various mixtures of Ar:O2: (i) 100:0 vol.%, (ii) 90:10 vol.%, (iii) 75:25 vol.%, (iv) 50:50 vol.%, and (v) 0:100 vol.%. Oxygen rich atmosphere was necessary to oxidize tin atoms. Self-design, simple high voltage power switch capable of charging the 20 µF capacitor bank from external high voltage power supply worked as a power supply for an unbalanced magnetron source. ITO thin films with thickness in the range of 30–40 nm were obtained after 300 deposition pulses of 900 V and deposition time of 900 s. The highest transmission of 88% at λ = 550 nm provided 0:100 vol. % Ar:O2 mixture, together with the lowest resistivity of 0.03 Ω·cm.


2011 ◽  
Vol 20 (01) ◽  
pp. 1-13 ◽  
Author(s):  
CHENCHANG ZHAN ◽  
WING-HUNG KI

A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low frequency, low quiescent current at light load and high bandwidth at heavy load. A prototype of the proposed high-PSR LDR is fabricated using a standard 0.35 μm CMOS process, occupying an active area of 0.066 mm2. The lowest supply voltage is 1.6 V and the preset output voltage is 1.2 V. The maximum load current is 10 mA. The measured worst-case PSR at full load without using large output capacitor is -22.7 dB up to 60 MHz. The line and load regulations are 0.25 mV/V and 0.32 mV/mA, respectively.


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