Protection Systems for Low Voltage, Low Power Systems

1998 ◽  
pp. 175-200
Author(s):  
Nihal Kularatna
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Low Voltage ◽  
Protection Systems

scholarly journals Low Power Contactless Voltage Sensor for Low Voltage Power Systems

Sensors ◽  
2019 ◽  
Vol 19 (16) ◽  
pp. 3513 ◽  
Author(s):  
Antonio Delle Femine ◽  
Daniele Gallo ◽  
Carmine Landi ◽  
Alessandro Lo Schiavo ◽  
Mario Luiso
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Good Accuracy ◽  
Low Voltage ◽  
Harmonic Distortion ◽  
Voltage Sensor ◽  
Power Cable ◽  
Voltage Measurement ◽  
Line Voltage ◽  
Capacitive Probe

Contactless measurements represent the desirable solution in many contexts, where minimal cabling is required or, in general, cabling is not possible. This paper presents a new contactless voltage sensor for low voltage power systems. It is based on a contactless capacitive probe, which surrounds the power cable. It has two concentric electrodes insulated by a shield. A low power analog conditioning circuit evaluates the power line voltage by measuring the current in one of the capacitances of the probe. All the single stages of the circuit have been designed by using low-power rail-to-rail operational amplifiers, supplied at 3.3 V, in order to minimize the power absorption. The sensor has been characterized in various conditions, with sine waves and distorted signals, varying the frequency and the harmonic distortion. The influence of the current, flowing into the power cable, on the voltage measurement has been evaluated too. It shows a good accuracy (lower than 0.3%) from 100 V to 300 V, with a power consumption less than 5 mW.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals Uncontrolled Electric Vehicle Charging Impacts on Distribution Electric Power Systems with Primarily Residential, Commercial or Industrial Loads

Energies ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1688 ◽  
Author(s):  
C. Birk Jones ◽  
Matthew Lave ◽  
William Vining ◽  
Brooke Marshall Garcia
Keyword(s):  
Power Systems ◽  
Electric Power ◽  
Low Voltage ◽  
Peak Load ◽  
Electric Power Systems ◽  
Primary System ◽  
Maximum Increase ◽  
Actual Distribution ◽  
The Impact ◽  
Ev Charging

An increase in Electric Vehicles (EV) will result in higher demands on the distribution electric power systems (EPS) which may result in thermal line overloading and low voltage violations. To understand the impact, this work simulates two EV charging scenarios (home- and work-dominant) under potential 2030 EV adoption levels on 10 actual distribution feeders that support residential, commercial, and industrial loads. The simulations include actual driving patterns of existing (non-EV) vehicles taken from global positioning system (GPS) data. The GPS driving behaviors, which explain the spatial and temporal EV charging demands, provide information on each vehicles travel distance, dwell locations, and dwell durations. Then, the EPS simulations incorporate the EV charging demands to calculate the power flow across the feeder. Simulation results show that voltage impacts are modest (less than 0.01 p.u.), likely due to robust feeder designs and the models only represent the high-voltage (“primary”) system components. Line loading impacts are more noticeable, with a maximum increase of about 15%. Additionally, the feeder peak load times experience a slight shift for residential and mixed feeders (≈1 h), not at all for the industrial, and 8 h for the commercial feeder.

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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